1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h] 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007 Atmel Corporation. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Memory Controllers (MATRIX, EBI) - System peripherals registers. 7*4882a593Smuzhiyun * Based on AT91SAM9260 datasheet revision B. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef AT91SAM9260_MATRIX_H 13*4882a593Smuzhiyun #define AT91SAM9260_MATRIX_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * This struct defines access to the matrix' maximum of 19*4882a593Smuzhiyun * 16 masters and 16 slaves. 20*4882a593Smuzhiyun * However, on the AT91SAM9260/9G20/9XE there exist only 21*4882a593Smuzhiyun * 6 Masters and 5 Slaves! 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun struct at91_matrix { 24*4882a593Smuzhiyun u32 mcfg[16]; /* Master Configuration Registers */ 25*4882a593Smuzhiyun u32 scfg[16]; /* Slave Configuration Registers */ 26*4882a593Smuzhiyun u32 pras[16][2]; /* Priority Assignment Slave Registers */ 27*4882a593Smuzhiyun u32 mrcr; /* Master Remap Control Register */ 28*4882a593Smuzhiyun u32 filler[0x06]; 29*4882a593Smuzhiyun u32 ebicsa; /* EBI Chip Select Assignment Register */ 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 35*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 36*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_FOUR (2 << 0) 37*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 38*4882a593Smuzhiyun #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 41*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 42*4882a593Smuzhiyun #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 43*4882a593Smuzhiyun #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 44*4882a593Smuzhiyun #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 45*4882a593Smuzhiyun #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define AT91_MATRIX_M0PR_SHIFT 0 48*4882a593Smuzhiyun #define AT91_MATRIX_M1PR_SHIFT 4 49*4882a593Smuzhiyun #define AT91_MATRIX_M2PR_SHIFT 8 50*4882a593Smuzhiyun #define AT91_MATRIX_M3PR_SHIFT 12 51*4882a593Smuzhiyun #define AT91_MATRIX_M4PR_SHIFT 16 52*4882a593Smuzhiyun #define AT91_MATRIX_M5PR_SHIFT 20 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define AT91_MATRIX_RCB0 (1 << 0) 55*4882a593Smuzhiyun #define AT91_MATRIX_RCB1 (1 << 1) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 58*4882a593Smuzhiyun #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) 59*4882a593Smuzhiyun #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) 60*4882a593Smuzhiyun #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) 61*4882a593Smuzhiyun #define AT91_MATRIX_DBPUC (1 << 8) 62*4882a593Smuzhiyun #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) 63*4882a593Smuzhiyun #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) 64*4882a593Smuzhiyun #define AT91_MATRIX_EBI_IOSR_SEL (1 << 17) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Maximum Number of Allowed Cycles for a Burst */ 67*4882a593Smuzhiyun #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) 68*4882a593Smuzhiyun #define AT91_MATRIX_SLOT_CYCLE_(x) (x << 0) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif 71