1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __AT91RM9200_H__ 7*4882a593Smuzhiyun #define __AT91RM9200_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define CONFIG_AT91FAMILY /* it's a member of AT91 family */ 10*4882a593Smuzhiyun #define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */ 11*4882a593Smuzhiyun #define CONFIG_AT91_GPIO /* and require always gpio features */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Periperial Identifiers */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define ATMEL_ID_SYS 1 /* System Peripheral */ 16*4882a593Smuzhiyun #define ATMEL_ID_PIOA 2 /* PIO port A */ 17*4882a593Smuzhiyun #define ATMEL_ID_PIOB 3 /* PIO port B */ 18*4882a593Smuzhiyun #define ATMEL_ID_PIOC 4 /* PIO port C */ 19*4882a593Smuzhiyun #define ATMEL_ID_PIOD 5 /* PIO port D BGA only */ 20*4882a593Smuzhiyun #define ATMEL_ID_USART0 6 /* USART 0 */ 21*4882a593Smuzhiyun #define ATMEL_ID_USART1 7 /* USART 1 */ 22*4882a593Smuzhiyun #define ATMEL_ID_USART2 8 /* USART 2 */ 23*4882a593Smuzhiyun #define ATMEL_ID_USART3 9 /* USART 3 */ 24*4882a593Smuzhiyun #define ATMEL_ID_MCI 10 /* Multimedia Card Interface */ 25*4882a593Smuzhiyun #define ATMEL_ID_UDP 11 /* USB Device Port */ 26*4882a593Smuzhiyun #define ATMEL_ID_TWI 12 /* Two Wire Interface */ 27*4882a593Smuzhiyun #define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */ 28*4882a593Smuzhiyun #define ATMEL_ID_SSC0 14 /* Synch. Serial Controller 0 */ 29*4882a593Smuzhiyun #define ATMEL_ID_SSC1 15 /* Synch. Serial Controller 1 */ 30*4882a593Smuzhiyun #define ATMEL_ID_SSC2 16 /* Synch. Serial Controller 2 */ 31*4882a593Smuzhiyun #define ATMEL_ID_TC0 17 /* Timer Counter 0 */ 32*4882a593Smuzhiyun #define ATMEL_ID_TC1 18 /* Timer Counter 1 */ 33*4882a593Smuzhiyun #define ATMEL_ID_TC2 19 /* Timer Counter 2 */ 34*4882a593Smuzhiyun #define ATMEL_ID_TC3 20 /* Timer Counter 3 */ 35*4882a593Smuzhiyun #define ATMEL_ID_TC4 21 /* Timer Counter 4 */ 36*4882a593Smuzhiyun #define ATMEL_ID_TC5 22 /* Timer Counter 5 */ 37*4882a593Smuzhiyun #define ATMEL_ID_UHP 23 /* OHCI USB Host Port */ 38*4882a593Smuzhiyun #define ATMEL_ID_EMAC 24 /* Ethernet MAC */ 39*4882a593Smuzhiyun #define ATMEL_ID_IRQ0 25 /* Advanced Interrupt Controller */ 40*4882a593Smuzhiyun #define ATMEL_ID_IRQ1 26 /* Advanced Interrupt Controller */ 41*4882a593Smuzhiyun #define ATMEL_ID_IRQ2 27 /* Advanced Interrupt Controller */ 42*4882a593Smuzhiyun #define ATMEL_ID_IRQ3 28 /* Advanced Interrupt Controller */ 43*4882a593Smuzhiyun #define ATMEL_ID_IRQ4 29 /* Advanced Interrupt Controller */ 44*4882a593Smuzhiyun #define ATMEL_ID_IRQ5 30 /* Advanced Interrupt Controller */ 45*4882a593Smuzhiyun #define ATMEL_ID_IRQ6 31 /* Advanced Interrupt Controller */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define ATMEL_USB_HOST_BASE 0x00300000 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define ATMEL_BASE_TC 0xFFFA0000 50*4882a593Smuzhiyun #define ATMEL_BASE_UDP 0xFFFB0000 51*4882a593Smuzhiyun #define ATMEL_BASE_MCI 0xFFFB4000 52*4882a593Smuzhiyun #define ATMEL_BASE_TWI 0xFFFB8000 53*4882a593Smuzhiyun #define ATMEL_BASE_EMAC 0xFFFBC000 54*4882a593Smuzhiyun #define ATMEL_BASE_USART 0xFFFC0000 /* 4x 0x4000 Offset */ 55*4882a593Smuzhiyun #define ATMEL_BASE_USART0 ATMEL_BASE_USART 56*4882a593Smuzhiyun #define ATMEL_BASE_USART1 (ATMEL_BASE_USART + 0x4000) 57*4882a593Smuzhiyun #define ATMEL_BASE_USART2 (ATMEL_BASE_USART + 0x8000) 58*4882a593Smuzhiyun #define ATMEL_BASE_USART3 (ATMEL_BASE_USART + 0xC000) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define ATMEL_BASE_SCC 0xFFFD0000 /* 4x 0x4000 Offset */ 61*4882a593Smuzhiyun #define ATMEL_BASE_SPI 0xFFFE0000 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define ATMEL_BASE_AIC 0xFFFFF000 64*4882a593Smuzhiyun #define ATMEL_BASE_DBGU 0xFFFFF200 65*4882a593Smuzhiyun #define ATMEL_BASE_PIO 0xFFFFF400 /* 4x 0x200 Offset */ 66*4882a593Smuzhiyun #define ATMEL_BASE_PIOA 0xFFFFF400 67*4882a593Smuzhiyun #define ATMEL_BASE_PIOB 0xFFFFF600 68*4882a593Smuzhiyun #define ATMEL_BASE_PIOC 0xFFFFF800 69*4882a593Smuzhiyun #define ATMEL_BASE_PIOD 0xFFFFFA00 70*4882a593Smuzhiyun #define ATMEL_BASE_PMC 0xFFFFFC00 71*4882a593Smuzhiyun #define ATMEL_BASE_ST 0xFFFFFD00 72*4882a593Smuzhiyun #define ATMEL_BASE_RTC 0xFFFFFE00 73*4882a593Smuzhiyun #define ATMEL_BASE_MC 0xFFFFFF00 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define AT91_PIO_BASE ATMEL_BASE_PIO 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* AT91RM9200 Periperial Multiplexing A */ 78*4882a593Smuzhiyun /* Port A */ 79*4882a593Smuzhiyun #define ATMEL_PMX_AA_EREFCK 0x00000080 80*4882a593Smuzhiyun #define ATMEL_PMX_AA_ETXCK 0x00000080 81*4882a593Smuzhiyun #define ATMEL_PMX_AA_ETXEN 0x00000100 82*4882a593Smuzhiyun #define ATMEL_PMX_AA_ETX0 0x00000200 83*4882a593Smuzhiyun #define ATMEL_PMX_AA_ETX1 0x00000400 84*4882a593Smuzhiyun #define ATMEL_PMX_AA_ECRS 0x00000800 85*4882a593Smuzhiyun #define ATMEL_PMX_AA_ECRSDV 0x00000800 86*4882a593Smuzhiyun #define ATMEL_PMX_AA_ERX0 0x00001000 87*4882a593Smuzhiyun #define ATMEL_PMX_AA_ERX1 0x00002000 88*4882a593Smuzhiyun #define ATMEL_PMX_AA_ERXER 0x00004000 89*4882a593Smuzhiyun #define ATMEL_PMX_AA_EMDC 0x00008000 90*4882a593Smuzhiyun #define ATMEL_PMX_AA_EMDIO 0x00010000 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define ATMEL_PMX_AA_TXD2 0x00800000 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define ATMEL_PMX_AA_TWD 0x02000000 95*4882a593Smuzhiyun #define ATMEL_PMX_AA_TWCK 0x04000000 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* Port B */ 98*4882a593Smuzhiyun #define ATMEL_PMX_BA_ERXCK 0x00080000 99*4882a593Smuzhiyun #define ATMEL_PMX_BA_ECOL 0x00040000 100*4882a593Smuzhiyun #define ATMEL_PMX_BA_ERXDV 0x00020000 101*4882a593Smuzhiyun #define ATMEL_PMX_BA_ERX3 0x00010000 102*4882a593Smuzhiyun #define ATMEL_PMX_BA_ERX2 0x00008000 103*4882a593Smuzhiyun #define ATMEL_PMX_BA_ETXER 0x00004000 104*4882a593Smuzhiyun #define ATMEL_PMX_BA_ETX3 0x00002000 105*4882a593Smuzhiyun #define ATMEL_PMX_BA_ETX2 0x00001000 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* Port B */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define ATMEL_PMX_CA_BFCK 0x00000001 110*4882a593Smuzhiyun #define ATMEL_PMX_CA_BFRDY 0x00000002 111*4882a593Smuzhiyun #define ATMEL_PMX_CA_SMOE 0x00000002 112*4882a593Smuzhiyun #define ATMEL_PMX_CA_BFAVD 0x00000004 113*4882a593Smuzhiyun #define ATMEL_PMX_CA_BFBAA 0x00000008 114*4882a593Smuzhiyun #define ATMEL_PMX_CA_SMWE 0x00000008 115*4882a593Smuzhiyun #define ATMEL_PMX_CA_BFOE 0x00000010 116*4882a593Smuzhiyun #define ATMEL_PMX_CA_BFWE 0x00000020 117*4882a593Smuzhiyun #define ATMEL_PMX_CA_NWAIT 0x00000040 118*4882a593Smuzhiyun #define ATMEL_PMX_CA_A23 0x00000080 119*4882a593Smuzhiyun #define ATMEL_PMX_CA_A24 0x00000100 120*4882a593Smuzhiyun #define ATMEL_PMX_CA_A25 0x00000200 121*4882a593Smuzhiyun #define ATMEL_PMX_CA_CFRNW 0x00000200 122*4882a593Smuzhiyun #define ATMEL_PMX_CA_NCS4 0x00000400 123*4882a593Smuzhiyun #define ATMEL_PMX_CA_CFCS 0x00000400 124*4882a593Smuzhiyun #define ATMEL_PMX_CA_NCS5 0x00000800 125*4882a593Smuzhiyun #define ATMEL_PMX_CA_CFCE1 0x00001000 126*4882a593Smuzhiyun #define ATMEL_PMX_CA_NCS6 0x00001000 127*4882a593Smuzhiyun #define ATMEL_PMX_CA_CFCE2 0x00002000 128*4882a593Smuzhiyun #define ATMEL_PMX_CA_NCS7 0x00002000 129*4882a593Smuzhiyun #define ATMEL_PMX_CA_D16_31 0xFFFF0000 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define ATMEL_PIO_PORTS 4 /* theese SoCs have 4 PIO */ 132*4882a593Smuzhiyun #define ATMEL_PMC_UHP AT91RM9200_PMC_UHP 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define CONFIG_SYS_ATMEL_CPU_NAME "AT91RM9200" 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #endif 137