1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef AT91_TC_H 8*4882a593Smuzhiyun #define AT91_TC_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun typedef struct at91_tcc { 11*4882a593Smuzhiyun u32 ccr; /* 0x00 Channel Control Register */ 12*4882a593Smuzhiyun u32 cmr; /* 0x04 Channel Mode Register */ 13*4882a593Smuzhiyun u32 reserved1[2]; 14*4882a593Smuzhiyun u32 cv; /* 0x10 Counter Value */ 15*4882a593Smuzhiyun u32 ra; /* 0x14 Register A */ 16*4882a593Smuzhiyun u32 rb; /* 0x18 Register B */ 17*4882a593Smuzhiyun u32 rc; /* 0x1C Register C */ 18*4882a593Smuzhiyun u32 sr; /* 0x20 Status Register */ 19*4882a593Smuzhiyun u32 ier; /* 0x24 Interrupt Enable Register */ 20*4882a593Smuzhiyun u32 idr; /* 0x28 Interrupt Disable Register */ 21*4882a593Smuzhiyun u32 imr; /* 0x2C Interrupt Mask Register */ 22*4882a593Smuzhiyun u32 reserved3[4]; 23*4882a593Smuzhiyun } at91_tcc_t; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define AT91_TC_CCR_CLKEN 0x00000001 26*4882a593Smuzhiyun #define AT91_TC_CCR_CLKDIS 0x00000002 27*4882a593Smuzhiyun #define AT91_TC_CCR_SWTRG 0x00000004 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define AT91_TC_CMR_CPCTRG 0x00004000 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000 32*4882a593Smuzhiyun #define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001 33*4882a593Smuzhiyun #define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002 34*4882a593Smuzhiyun #define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003 35*4882a593Smuzhiyun #define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004 36*4882a593Smuzhiyun #define AT91_TC_CMR_TCCLKS_XC0 0x00000005 37*4882a593Smuzhiyun #define AT91_TC_CMR_TCCLKS_XC1 0x00000006 38*4882a593Smuzhiyun #define AT91_TC_CMR_TCCLKS_XC2 0x00000007 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun typedef struct at91_tc { 41*4882a593Smuzhiyun at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */ 42*4882a593Smuzhiyun u32 bcr; /* 0xC0 TC Block Control Register */ 43*4882a593Smuzhiyun u32 bmr; /* 0xC4 TC Block Mode Register */ 44*4882a593Smuzhiyun } at91_tc_t; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000 47*4882a593Smuzhiyun #define AT91_TC_BMR_TC0XC0S_NONE 0x00000001 48*4882a593Smuzhiyun #define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002 49*4882a593Smuzhiyun #define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000 52*4882a593Smuzhiyun #define AT91_TC_BMR_TC1XC1S_NONE 0x00000004 53*4882a593Smuzhiyun #define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008 54*4882a593Smuzhiyun #define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000 57*4882a593Smuzhiyun #define AT91_TC_BMR_TC2XC2S_NONE 0x00000010 58*4882a593Smuzhiyun #define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020 59*4882a593Smuzhiyun #define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif 62