1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007 Andrew Victor 5*4882a593Smuzhiyun * Copyright (C) 2007 Atmel Corporation. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Reset Controller (RSTC) - System peripherals regsters. 8*4882a593Smuzhiyun * Based on AT91SAM9261 datasheet revision D. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef AT91_RSTC_H 14*4882a593Smuzhiyun #define AT91_RSTC_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Reset Controller Status Register */ 17*4882a593Smuzhiyun #define AT91_ASM_RSTC_SR (ATMEL_BASE_RSTC + 0x04) 18*4882a593Smuzhiyun #define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun typedef struct at91_rstc { 23*4882a593Smuzhiyun u32 cr; /* Reset Controller Control Register */ 24*4882a593Smuzhiyun u32 sr; /* Reset Controller Status Register */ 25*4882a593Smuzhiyun u32 mr; /* Reset Controller Mode Register */ 26*4882a593Smuzhiyun } at91_rstc_t; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define AT91_RSTC_KEY 0xA5000000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define AT91_RSTC_CR_PROCRST 0x00000001 33*4882a593Smuzhiyun #define AT91_RSTC_CR_PERRST 0x00000004 34*4882a593Smuzhiyun #define AT91_RSTC_CR_EXTRST 0x00000008 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define AT91_RSTC_MR_URSTEN 0x00000001 37*4882a593Smuzhiyun #define AT91_RSTC_MR_URSTIEN 0x00000010 38*4882a593Smuzhiyun #define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8) 39*4882a593Smuzhiyun #define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define AT91_RSTC_SR_NRSTL 0x00010000 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ 44*4882a593Smuzhiyun #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) 45*4882a593Smuzhiyun #define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) 46*4882a593Smuzhiyun #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) 47*4882a593Smuzhiyun #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) 48*4882a593Smuzhiyun #define AT91_RSTC_RSTTYP_USER (4 << 8) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif 51