1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC)) 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef AT91_H 10*4882a593Smuzhiyun #define AT91_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun typedef struct at91_emac { 13*4882a593Smuzhiyun u32 ctl; 14*4882a593Smuzhiyun u32 cfg; 15*4882a593Smuzhiyun u32 sr; 16*4882a593Smuzhiyun u32 tar; 17*4882a593Smuzhiyun u32 tcr; 18*4882a593Smuzhiyun u32 tsr; 19*4882a593Smuzhiyun u32 rbqp; 20*4882a593Smuzhiyun u32 reserved0; 21*4882a593Smuzhiyun u32 rsr; 22*4882a593Smuzhiyun u32 isr; 23*4882a593Smuzhiyun u32 ier; 24*4882a593Smuzhiyun u32 idr; 25*4882a593Smuzhiyun u32 imr; 26*4882a593Smuzhiyun u32 man; 27*4882a593Smuzhiyun u32 reserved1[2]; 28*4882a593Smuzhiyun u32 fra; 29*4882a593Smuzhiyun u32 scol; 30*4882a593Smuzhiyun u32 mocl; 31*4882a593Smuzhiyun u32 ok; 32*4882a593Smuzhiyun u32 seqe; 33*4882a593Smuzhiyun u32 ale; 34*4882a593Smuzhiyun u32 dte; 35*4882a593Smuzhiyun u32 lcol; 36*4882a593Smuzhiyun u32 ecol; 37*4882a593Smuzhiyun u32 cse; 38*4882a593Smuzhiyun u32 tue; 39*4882a593Smuzhiyun u32 cde; 40*4882a593Smuzhiyun u32 elr; 41*4882a593Smuzhiyun u32 rjb; 42*4882a593Smuzhiyun u32 usf; 43*4882a593Smuzhiyun u32 sqee; 44*4882a593Smuzhiyun u32 drfc; 45*4882a593Smuzhiyun u32 reserved2[3]; 46*4882a593Smuzhiyun u32 hsh; 47*4882a593Smuzhiyun u32 hsl; 48*4882a593Smuzhiyun u32 sa1l; 49*4882a593Smuzhiyun u32 sa1h; 50*4882a593Smuzhiyun u32 sa2l; 51*4882a593Smuzhiyun u32 sa2h; 52*4882a593Smuzhiyun u32 sa3l; 53*4882a593Smuzhiyun u32 sa3h; 54*4882a593Smuzhiyun u32 sa4l; 55*4882a593Smuzhiyun u32 sa4h; 56*4882a593Smuzhiyun } at91_emac_t; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define AT91_EMAC_CTL_LB 0x0001 59*4882a593Smuzhiyun #define AT91_EMAC_CTL_LBL 0x0002 60*4882a593Smuzhiyun #define AT91_EMAC_CTL_RE 0x0004 61*4882a593Smuzhiyun #define AT91_EMAC_CTL_TE 0x0008 62*4882a593Smuzhiyun #define AT91_EMAC_CTL_MPE 0x0010 63*4882a593Smuzhiyun #define AT91_EMAC_CTL_CSR 0x0020 64*4882a593Smuzhiyun #define AT91_EMAC_CTL_ISR 0x0040 65*4882a593Smuzhiyun #define AT91_EMAC_CTL_WES 0x0080 66*4882a593Smuzhiyun #define AT91_EMAC_CTL_BP 0x1000 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define AT91_EMAC_CFG_SPD 0x0001 69*4882a593Smuzhiyun #define AT91_EMAC_CFG_FD 0x0002 70*4882a593Smuzhiyun #define AT91_EMAC_CFG_BR 0x0004 71*4882a593Smuzhiyun #define AT91_EMAC_CFG_CAF 0x0010 72*4882a593Smuzhiyun #define AT91_EMAC_CFG_NBC 0x0020 73*4882a593Smuzhiyun #define AT91_EMAC_CFG_MTI 0x0040 74*4882a593Smuzhiyun #define AT91_EMAC_CFG_UNI 0x0080 75*4882a593Smuzhiyun #define AT91_EMAC_CFG_BIG 0x0100 76*4882a593Smuzhiyun #define AT91_EMAC_CFG_EAE 0x0200 77*4882a593Smuzhiyun #define AT91_EMAC_CFG_CLK_MASK 0xFFFFF3FF 78*4882a593Smuzhiyun #define AT91_EMAC_CFG_MCLK_8 0x0000 79*4882a593Smuzhiyun #define AT91_EMAC_CFG_MCLK_16 0x0400 80*4882a593Smuzhiyun #define AT91_EMAC_CFG_MCLK_32 0x0800 81*4882a593Smuzhiyun #define AT91_EMAC_CFG_MCLK_64 0x0C00 82*4882a593Smuzhiyun #define AT91_EMAC_CFG_RTY 0x1000 83*4882a593Smuzhiyun #define AT91_EMAC_CFG_RMII 0x2000 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define AT91_EMAC_SR_LINK 0x0001 86*4882a593Smuzhiyun #define AT91_EMAC_SR_MDIO 0x0002 87*4882a593Smuzhiyun #define AT91_EMAC_SR_IDLE 0x0004 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define AT91_EMAC_TCR_LEN(x) (x & 0x7FF) 90*4882a593Smuzhiyun #define AT91_EMAC_TCR_NCRC 0x8000 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define AT91_EMAC_TSR_OVR 0x0001 93*4882a593Smuzhiyun #define AT91_EMAC_TSR_COL 0x0002 94*4882a593Smuzhiyun #define AT91_EMAC_TSR_RLE 0x0004 95*4882a593Smuzhiyun #define AT91_EMAC_TSR_TXIDLE 0x0008 96*4882a593Smuzhiyun #define AT91_EMAC_TSR_BNQ 0x0010 97*4882a593Smuzhiyun #define AT91_EMAC_TSR_COMP 0x0020 98*4882a593Smuzhiyun #define AT91_EMAC_TSR_UND 0x0040 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define AT91_EMAC_RSR_BNA 0x0001 101*4882a593Smuzhiyun #define AT91_EMAC_RSR_REC 0x0002 102*4882a593Smuzhiyun #define AT91_EMAC_RSR_OVR 0x0004 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* ISR, IER, IDR, IMR use the same bits */ 105*4882a593Smuzhiyun #define AT91_EMAC_IxR_DONE 0x0001 106*4882a593Smuzhiyun #define AT91_EMAC_IxR_RCOM 0x0002 107*4882a593Smuzhiyun #define AT91_EMAC_IxR_RBNA 0x0004 108*4882a593Smuzhiyun #define AT91_EMAC_IxR_TOVR 0x0008 109*4882a593Smuzhiyun #define AT91_EMAC_IxR_TUND 0x0010 110*4882a593Smuzhiyun #define AT91_EMAC_IxR_RTRY 0x0020 111*4882a593Smuzhiyun #define AT91_EMAC_IxR_TBRE 0x0040 112*4882a593Smuzhiyun #define AT91_EMAC_IxR_TCOM 0x0080 113*4882a593Smuzhiyun #define AT91_EMAC_IxR_TIDLE 0x0100 114*4882a593Smuzhiyun #define AT91_EMAC_IxR_LINK 0x0200 115*4882a593Smuzhiyun #define AT91_EMAC_IxR_ROVR 0x0400 116*4882a593Smuzhiyun #define AT91_EMAC_IxR_HRESP 0x0800 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define AT91_EMAC_MAN_DATA_MASK 0xFFFF 119*4882a593Smuzhiyun #define AT91_EMAC_MAN_CODE_802_3 0x00020000 120*4882a593Smuzhiyun #define AT91_EMAC_MAN_REGA(reg) ((reg & 0x1F) << 18) 121*4882a593Smuzhiyun #define AT91_EMAC_MAN_PHYA(phy) ((phy & 0x1F) << 23) 122*4882a593Smuzhiyun #define AT91_EMAC_MAN_RW_R 0x20000000 123*4882a593Smuzhiyun #define AT91_EMAC_MAN_RW_W 0x10000000 124*4882a593Smuzhiyun #define AT91_EMAC_MAN_HIGH 0x40000000 125*4882a593Smuzhiyun #define AT91_EMAC_MAN_LOW 0x80000000 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #endif 128