1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2010 3*4882a593Smuzhiyun * Reinhard Meyer, reinhard.meyer@emk-elektronik.de 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Enhanced Embedded Flash Controller 6*4882a593Smuzhiyun * Based on AT91SAM9XE datasheet 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef AT91_EEFC_H 12*4882a593Smuzhiyun #define AT91_EEFC_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun typedef struct at91_eefc { 17*4882a593Smuzhiyun u32 fmr; /* Flash Mode Register RW */ 18*4882a593Smuzhiyun u32 fcr; /* Flash Command Register WO */ 19*4882a593Smuzhiyun u32 fsr; /* Flash Status Register RO */ 20*4882a593Smuzhiyun u32 frr; /* Flash Result Register RO */ 21*4882a593Smuzhiyun } at91_eefc_t; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define AT91_EEFC_FMR_FWS_MASK 0x00000f00 26*4882a593Smuzhiyun #define AT91_EEFC_FMR_FRDY_BIT 0x00000001 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define AT91_EEFC_FCR_KEY 0x5a000000 29*4882a593Smuzhiyun #define AT91_EEFC_FCR_FARG_MASK 0x00ffff00 30*4882a593Smuzhiyun #define AT91_EEFC_FCR_FARG_SHIFT 8 31*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_GETD 0x0 32*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_WP 0x1 33*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_WPL 0x2 34*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_EWP 0x3 35*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_EWPL 0x4 36*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_EA 0x5 37*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_SLB 0x8 38*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_CLB 0x9 39*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_GLB 0xA 40*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_SGPB 0xB 41*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_CGPB 0xC 42*4882a593Smuzhiyun #define AT91_EEFC_FCR_FCMD_GGPB 0xD 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define AT91_EEFC_FSR_FRDY 1 45*4882a593Smuzhiyun #define AT91_EEFC_FSR_FCMDE 2 46*4882a593Smuzhiyun #define AT91_EEFC_FSR_FLOCKE 4 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif 49