1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2010 3*4882a593Smuzhiyun * Reinhard Meyer, reinhard.meyer@emk-elektronik.de 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Debug Unit 6*4882a593Smuzhiyun * Based on AT91SAM9XE datasheet 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef AT91_DBU_H 12*4882a593Smuzhiyun #define AT91_DBU_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun typedef struct at91_dbu { 17*4882a593Smuzhiyun u32 cr; /* Control Register WO */ 18*4882a593Smuzhiyun u32 mr; /* Mode Register RW */ 19*4882a593Smuzhiyun u32 ier; /* Interrupt Enable Register WO */ 20*4882a593Smuzhiyun u32 idr; /* Interrupt Disable Register WO */ 21*4882a593Smuzhiyun u32 imr; /* Interrupt Mask Register RO */ 22*4882a593Smuzhiyun u32 sr; /* Status Register RO */ 23*4882a593Smuzhiyun u32 rhr; /* Receive Holding Register RO */ 24*4882a593Smuzhiyun u32 thr; /* Transmit Holding Register WO */ 25*4882a593Smuzhiyun u32 brgr; /* Baud Rate Generator Register RW */ 26*4882a593Smuzhiyun u32 res1[7];/* 0x0024 - 0x003C Reserved */ 27*4882a593Smuzhiyun u32 cidr; /* Chip ID Register RO */ 28*4882a593Smuzhiyun u32 exid; /* Chip ID Extension Register RO */ 29*4882a593Smuzhiyun u32 fnr; /* Force NTRST Register RW */ 30*4882a593Smuzhiyun } at91_dbu_t; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AT91_DBU_CID_ARCH_MASK 0x0ff00000 35*4882a593Smuzhiyun #define AT91_DBU_CID_ARCH_9xx 0x01900000 36*4882a593Smuzhiyun #define AT91_DBU_CID_ARCH_9XExx 0x02900000 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif 39