1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 3*4882a593Smuzhiyun * Reinhard Meyer, reinhard.meyer@emk-elektronik.de 4*4882a593Smuzhiyun * (C) Copyright 2009 5*4882a593Smuzhiyun * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 6*4882a593Smuzhiyun * (C) Copyright 2013 7*4882a593Smuzhiyun * Bo Shen <voice.shen@atmel.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <common.h> 13*4882a593Smuzhiyun #include <asm/io.h> 14*4882a593Smuzhiyun #include <asm/arch/hardware.h> 15*4882a593Smuzhiyun #include <asm/arch/at91_pit.h> 16*4882a593Smuzhiyun #include <asm/arch/at91_gpbr.h> 17*4882a593Smuzhiyun #include <asm/arch/clk.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef CONFIG_SYS_AT91_MAIN_CLOCK 20*4882a593Smuzhiyun #define CONFIG_SYS_AT91_MAIN_CLOCK 0 21*4882a593Smuzhiyun #endif 22*4882a593Smuzhiyun arch_cpu_init(void)23*4882a593Smuzhiyunint arch_cpu_init(void) 24*4882a593Smuzhiyun { 25*4882a593Smuzhiyun return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); 26*4882a593Smuzhiyun } 27*4882a593Smuzhiyun arch_preboot_os(void)28*4882a593Smuzhiyunvoid arch_preboot_os(void) 29*4882a593Smuzhiyun { 30*4882a593Smuzhiyun ulong cpiv; 31*4882a593Smuzhiyun at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir)); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * Disable PITC 37*4882a593Smuzhiyun * Add 0x1000 to current counter to stop it faster 38*4882a593Smuzhiyun * without waiting for wrapping back to 0 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun writel(cpiv + 0x1000, &pit->mr); 41*4882a593Smuzhiyun } 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #if defined(CONFIG_DISPLAY_CPUINFO) print_cpuinfo(void)44*4882a593Smuzhiyunint print_cpuinfo(void) 45*4882a593Smuzhiyun { 46*4882a593Smuzhiyun char buf[32]; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun printf("CPU: %s\n", get_cpu_name()); 49*4882a593Smuzhiyun printf("Crystal frequency: %8s MHz\n", 50*4882a593Smuzhiyun strmhz(buf, get_main_clk_rate())); 51*4882a593Smuzhiyun printf("CPU clock : %8s MHz\n", 52*4882a593Smuzhiyun strmhz(buf, get_cpu_clk_rate())); 53*4882a593Smuzhiyun printf("Master clock : %8s MHz\n", 54*4882a593Smuzhiyun strmhz(buf, get_mck_clk_rate())); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun return 0; 57*4882a593Smuzhiyun } 58*4882a593Smuzhiyun #endif 59*4882a593Smuzhiyun enable_caches(void)60*4882a593Smuzhiyunvoid enable_caches(void) 61*4882a593Smuzhiyun { 62*4882a593Smuzhiyun icache_enable(); 63*4882a593Smuzhiyun dcache_enable(); 64*4882a593Smuzhiyun } 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define ATMEL_CHIPID_CIDR_VERSION 0x1f 67*4882a593Smuzhiyun get_chip_id(void)68*4882a593Smuzhiyununsigned int get_chip_id(void) 69*4882a593Smuzhiyun { 70*4882a593Smuzhiyun return readl(ATMEL_CHIPID_CIDR) & ~ATMEL_CHIPID_CIDR_VERSION; 71*4882a593Smuzhiyun } 72*4882a593Smuzhiyun get_extension_chip_id(void)73*4882a593Smuzhiyununsigned int get_extension_chip_id(void) 74*4882a593Smuzhiyun { 75*4882a593Smuzhiyun return readl(ATMEL_CHIPID_EXID); 76*4882a593Smuzhiyun } 77