1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2015 Atmel Corporation 3*4882a593Smuzhiyun * Bo Shen <voice.shen@atmel.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunMEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ 9*4882a593Smuzhiyun LENGTH = CONFIG_SPL_MAX_SIZE } 10*4882a593SmuzhiyunMEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ 11*4882a593Smuzhiyun LENGTH = CONFIG_SPL_BSS_MAX_SIZE } 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunOUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 14*4882a593SmuzhiyunOUTPUT_ARCH(arm) 15*4882a593SmuzhiyunENTRY(_start) 16*4882a593SmuzhiyunSECTIONS 17*4882a593Smuzhiyun{ 18*4882a593Smuzhiyun .text : 19*4882a593Smuzhiyun { 20*4882a593Smuzhiyun __start = .; 21*4882a593Smuzhiyun *(.vectors) 22*4882a593Smuzhiyun arch/arm/cpu/arm926ejs/start.o (.text*) 23*4882a593Smuzhiyun *(.text*) 24*4882a593Smuzhiyun } >.sram 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun . = ALIGN(4); 27*4882a593Smuzhiyun .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun . = ALIGN(4); 30*4882a593Smuzhiyun .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun . = ALIGN(4); 33*4882a593Smuzhiyun .u_boot_list : { KEEP(*(SORT(.u_boot_list*))) } > .sram 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun . = ALIGN(4); 36*4882a593Smuzhiyun __image_copy_end = .; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun .end : 39*4882a593Smuzhiyun { 40*4882a593Smuzhiyun *(.__end) 41*4882a593Smuzhiyun } >.sram 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun .bss : 44*4882a593Smuzhiyun { 45*4882a593Smuzhiyun . = ALIGN(4); 46*4882a593Smuzhiyun __bss_start = .; 47*4882a593Smuzhiyun *(.bss*) 48*4882a593Smuzhiyun . = ALIGN(4); 49*4882a593Smuzhiyun __bss_end = .; 50*4882a593Smuzhiyun } >.sdram 51*4882a593Smuzhiyun} 52