1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2007-2008 3*4882a593Smuzhiyun * Stelian Pop <stelian@popies.net> 4*4882a593Smuzhiyun * Lead Tech Design <www.leadtechdesign.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun #include <asm/io.h> 11*4882a593Smuzhiyun #include <asm/arch/hardware.h> 12*4882a593Smuzhiyun #include <asm/arch/at91_pit.h> 13*4882a593Smuzhiyun #include <asm/arch/clk.h> 14*4882a593Smuzhiyun #include <div64.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #if !defined(CONFIG_AT91FAMILY) 17*4882a593Smuzhiyun # error You need to define CONFIG_AT91FAMILY in your board config! 18*4882a593Smuzhiyun #endif 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by 24*4882a593Smuzhiyun * setting the 20 bit counter period to its maximum (0xfffff). 25*4882a593Smuzhiyun * (See the relevant data sheets to understand that this really works) 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * We do also mimic the typical powerpc way of incrementing 28*4882a593Smuzhiyun * two 32 bit registers called tbl and tbu. 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * Those registers increment at 1/16 the main clock rate. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define TIMER_LOAD_VAL 0xfffff 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * Use the PITC in full 32 bit incrementing mode 37*4882a593Smuzhiyun */ timer_init(void)38*4882a593Smuzhiyunint timer_init(void) 39*4882a593Smuzhiyun { 40*4882a593Smuzhiyun at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_SYS); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Enable PITC */ 45*4882a593Smuzhiyun writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun return 0; 50*4882a593Smuzhiyun } 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * Return the number of timer ticks per second. 54*4882a593Smuzhiyun */ get_tbclk(void)55*4882a593Smuzhiyunulong get_tbclk(void) 56*4882a593Smuzhiyun { 57*4882a593Smuzhiyun return gd->arch.timer_rate_hz; 58*4882a593Smuzhiyun } 59