1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Memory Setup stuff - taken from blob memsetup.S 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and 5*4882a593Smuzhiyun * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) 8*4882a593Smuzhiyun * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <config.h> 14*4882a593Smuzhiyun#include <asm/arch/hardware.h> 15*4882a593Smuzhiyun#include <asm/arch/at91_pmc.h> 16*4882a593Smuzhiyun#include <asm/arch/at91_wdt.h> 17*4882a593Smuzhiyun#include <asm/arch/at91_pio.h> 18*4882a593Smuzhiyun#include <asm/arch/at91_matrix.h> 19*4882a593Smuzhiyun#include <asm/arch/at91sam9_sdramc.h> 20*4882a593Smuzhiyun#include <asm/arch/at91sam9_smc.h> 21*4882a593Smuzhiyun#include <asm/arch/at91_rstc.h> 22*4882a593Smuzhiyun#ifdef CONFIG_ATMEL_LEGACY 23*4882a593Smuzhiyun#include <asm/arch/at91sam9_matrix.h> 24*4882a593Smuzhiyun#endif 25*4882a593Smuzhiyun#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL 26*4882a593Smuzhiyun#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL 27*4882a593Smuzhiyun#endif 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun.globl lowlevel_init 30*4882a593Smuzhiyun.type lowlevel_init,function 31*4882a593Smuzhiyunlowlevel_init: 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunPOS1: 34*4882a593Smuzhiyun adr r5, POS1 /* r5 = POS1 run time */ 35*4882a593Smuzhiyun ldr r0, =POS1 /* r0 = POS1 compile */ 36*4882a593Smuzhiyun sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* memory control configuration 1 */ 39*4882a593Smuzhiyun ldr r0, =SMRDATA 40*4882a593Smuzhiyun ldr r2, =SMRDATA1 41*4882a593Smuzhiyun add r0, r0, r5 42*4882a593Smuzhiyun add r2, r2, r5 43*4882a593Smuzhiyun0: 44*4882a593Smuzhiyun /* the address */ 45*4882a593Smuzhiyun ldr r1, [r0], #4 46*4882a593Smuzhiyun /* the value */ 47*4882a593Smuzhiyun ldr r3, [r0], #4 48*4882a593Smuzhiyun str r3, [r1] 49*4882a593Smuzhiyun cmp r2, r0 50*4882a593Smuzhiyun bne 0b 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun/* ---------------------------------------------------------------------------- 53*4882a593Smuzhiyun * PMC Init Step 1. 54*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 55*4882a593Smuzhiyun * - Check if the PLL is already initialized 56*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun ldr r1, =(AT91_ASM_PMC_MCKR) 59*4882a593Smuzhiyun ldr r0, [r1] 60*4882a593Smuzhiyun and r0, r0, #3 61*4882a593Smuzhiyun cmp r0, #0 62*4882a593Smuzhiyun bne PLL_setup_end 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun/* --------------------------------------------------------------------------- 65*4882a593Smuzhiyun * - Enable the Main Oscillator 66*4882a593Smuzhiyun * --------------------------------------------------------------------------- 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun ldr r1, =(AT91_ASM_PMC_MOR) 69*4882a593Smuzhiyun ldr r2, =(AT91_ASM_PMC_SR) 70*4882a593Smuzhiyun /* Main oscillator Enable register PMC_MOR: */ 71*4882a593Smuzhiyun ldr r0, =CONFIG_SYS_MOR_VAL 72*4882a593Smuzhiyun str r0, [r1] 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Reading the PMC Status to detect when the Main Oscillator is enabled */ 75*4882a593Smuzhiyun mov r4, #AT91_PMC_IXR_MOSCS 76*4882a593SmuzhiyunMOSCS_Loop: 77*4882a593Smuzhiyun ldr r3, [r2] 78*4882a593Smuzhiyun and r3, r4, r3 79*4882a593Smuzhiyun cmp r3, #AT91_PMC_IXR_MOSCS 80*4882a593Smuzhiyun bne MOSCS_Loop 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun/* ---------------------------------------------------------------------------- 83*4882a593Smuzhiyun * PMC Init Step 2. 84*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 85*4882a593Smuzhiyun * Setup PLLA 86*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun ldr r1, =(AT91_ASM_PMC_PLLAR) 89*4882a593Smuzhiyun ldr r0, =CONFIG_SYS_PLLAR_VAL 90*4882a593Smuzhiyun str r0, [r1] 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Reading the PMC Status register to detect when the PLLA is locked */ 93*4882a593Smuzhiyun mov r4, #AT91_PMC_IXR_LOCKA 94*4882a593SmuzhiyunMOSCS_Loop1: 95*4882a593Smuzhiyun ldr r3, [r2] 96*4882a593Smuzhiyun and r3, r4, r3 97*4882a593Smuzhiyun cmp r3, #AT91_PMC_IXR_LOCKA 98*4882a593Smuzhiyun bne MOSCS_Loop1 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun/* ---------------------------------------------------------------------------- 101*4882a593Smuzhiyun * PMC Init Step 3. 102*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 103*4882a593Smuzhiyun * - Switch on the Main Oscillator 104*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 105*4882a593Smuzhiyun */ 106*4882a593Smuzhiyun ldr r1, =(AT91_ASM_PMC_MCKR) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* -Master Clock Controller register PMC_MCKR */ 109*4882a593Smuzhiyun ldr r0, =CONFIG_SYS_MCKR1_VAL 110*4882a593Smuzhiyun str r0, [r1] 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* Reading the PMC Status to detect when the Master clock is ready */ 113*4882a593Smuzhiyun mov r4, #AT91_PMC_IXR_MCKRDY 114*4882a593SmuzhiyunMCKRDY_Loop: 115*4882a593Smuzhiyun ldr r3, [r2] 116*4882a593Smuzhiyun and r3, r4, r3 117*4882a593Smuzhiyun cmp r3, #AT91_PMC_IXR_MCKRDY 118*4882a593Smuzhiyun bne MCKRDY_Loop 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun ldr r0, =CONFIG_SYS_MCKR2_VAL 121*4882a593Smuzhiyun str r0, [r1] 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* Reading the PMC Status to detect when the Master clock is ready */ 124*4882a593Smuzhiyun mov r4, #AT91_PMC_IXR_MCKRDY 125*4882a593SmuzhiyunMCKRDY_Loop1: 126*4882a593Smuzhiyun ldr r3, [r2] 127*4882a593Smuzhiyun and r3, r4, r3 128*4882a593Smuzhiyun cmp r3, #AT91_PMC_IXR_MCKRDY 129*4882a593Smuzhiyun bne MCKRDY_Loop1 130*4882a593SmuzhiyunPLL_setup_end: 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun/* ---------------------------------------------------------------------------- 133*4882a593Smuzhiyun * - memory control configuration 2 134*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 135*4882a593Smuzhiyun */ 136*4882a593Smuzhiyun ldr r0, =(AT91_ASM_SDRAMC_TR) 137*4882a593Smuzhiyun ldr r1, [r0] 138*4882a593Smuzhiyun cmp r1, #0 139*4882a593Smuzhiyun bne SDRAM_setup_end 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun ldr r0, =SMRDATA1 142*4882a593Smuzhiyun ldr r2, =SMRDATA2 143*4882a593Smuzhiyun add r0, r0, r5 144*4882a593Smuzhiyun add r2, r2, r5 145*4882a593Smuzhiyun2: 146*4882a593Smuzhiyun /* the address */ 147*4882a593Smuzhiyun ldr r1, [r0], #4 148*4882a593Smuzhiyun /* the value */ 149*4882a593Smuzhiyun ldr r3, [r0], #4 150*4882a593Smuzhiyun str r3, [r1] 151*4882a593Smuzhiyun cmp r2, r0 152*4882a593Smuzhiyun bne 2b 153*4882a593Smuzhiyun 154*4882a593SmuzhiyunSDRAM_setup_end: 155*4882a593Smuzhiyun /* everything is fine now */ 156*4882a593Smuzhiyun mov pc, lr 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun .ltorg 159*4882a593Smuzhiyun 160*4882a593SmuzhiyunSMRDATA: 161*4882a593Smuzhiyun .word AT91_ASM_WDT_MR 162*4882a593Smuzhiyun .word CONFIG_SYS_WDTC_WDMR_VAL 163*4882a593Smuzhiyun /* configure PIOx as EBI0 D[16-31] */ 164*4882a593Smuzhiyun#if defined(CONFIG_AT91SAM9263) 165*4882a593Smuzhiyun .word AT91_ASM_PIOD_PDR 166*4882a593Smuzhiyun .word CONFIG_SYS_PIOD_PDR_VAL1 167*4882a593Smuzhiyun .word AT91_ASM_PIOD_PUDR 168*4882a593Smuzhiyun .word CONFIG_SYS_PIOD_PPUDR_VAL 169*4882a593Smuzhiyun .word AT91_ASM_PIOD_ASR 170*4882a593Smuzhiyun .word CONFIG_SYS_PIOD_PPUDR_VAL 171*4882a593Smuzhiyun#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ 172*4882a593Smuzhiyun || defined(CONFIG_AT91SAM9G20) 173*4882a593Smuzhiyun .word AT91_ASM_PIOC_PDR 174*4882a593Smuzhiyun .word CONFIG_SYS_PIOC_PDR_VAL1 175*4882a593Smuzhiyun .word AT91_ASM_PIOC_PUDR 176*4882a593Smuzhiyun .word CONFIG_SYS_PIOC_PPUDR_VAL 177*4882a593Smuzhiyun#endif 178*4882a593Smuzhiyun .word AT91_ASM_MATRIX_CSA0 179*4882a593Smuzhiyun .word CONFIG_SYS_MATRIX_EBICSA_VAL 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* flash */ 182*4882a593Smuzhiyun .word AT91_ASM_SMC_MODE0 183*4882a593Smuzhiyun .word CONFIG_SYS_SMC0_MODE0_VAL 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun .word AT91_ASM_SMC_CYCLE0 186*4882a593Smuzhiyun .word CONFIG_SYS_SMC0_CYCLE0_VAL 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun .word AT91_ASM_SMC_PULSE0 189*4882a593Smuzhiyun .word CONFIG_SYS_SMC0_PULSE0_VAL 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun .word AT91_ASM_SMC_SETUP0 192*4882a593Smuzhiyun .word CONFIG_SYS_SMC0_SETUP0_VAL 193*4882a593Smuzhiyun 194*4882a593SmuzhiyunSMRDATA1: 195*4882a593Smuzhiyun .word AT91_ASM_SDRAMC_MR 196*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_MR_VAL1 197*4882a593Smuzhiyun .word AT91_ASM_SDRAMC_TR 198*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_TR_VAL1 199*4882a593Smuzhiyun .word AT91_ASM_SDRAMC_CR 200*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_CR_VAL 201*4882a593Smuzhiyun .word AT91_ASM_SDRAMC_MDR 202*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_MDR_VAL 203*4882a593Smuzhiyun .word AT91_ASM_SDRAMC_MR 204*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_MR_VAL2 205*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 206*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL1 207*4882a593Smuzhiyun .word AT91_ASM_SDRAMC_MR 208*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_MR_VAL3 209*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 210*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL2 211*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 212*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL3 213*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 214*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL4 215*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 216*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL5 217*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 218*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL6 219*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 220*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL7 221*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 222*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL8 223*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 224*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL9 225*4882a593Smuzhiyun .word AT91_ASM_SDRAMC_MR 226*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_MR_VAL4 227*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 228*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL10 229*4882a593Smuzhiyun .word AT91_ASM_SDRAMC_MR 230*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_MR_VAL5 231*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 232*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL11 233*4882a593Smuzhiyun .word AT91_ASM_SDRAMC_TR 234*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_TR_VAL2 235*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_BASE 236*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL12 237*4882a593Smuzhiyun /* User reset enable*/ 238*4882a593Smuzhiyun .word AT91_ASM_RSTC_MR 239*4882a593Smuzhiyun .word CONFIG_SYS_RSTC_RMR_VAL 240*4882a593Smuzhiyun#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP 241*4882a593Smuzhiyun /* MATRIX_MCFG - REMAP all masters */ 242*4882a593Smuzhiyun .word AT91_ASM_MATRIX_MCFG 243*4882a593Smuzhiyun .word 0x1FF 244*4882a593Smuzhiyun#endif 245*4882a593SmuzhiyunSMRDATA2: 246*4882a593Smuzhiyun .word 0 247