1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2007-2008
3*4882a593Smuzhiyun * Stelian Pop <stelian@popies.net>
4*4882a593Smuzhiyun * Lead Tech Design <www.leadtechdesign.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch/at91_common.h>
12*4882a593Smuzhiyun #include <asm/arch/clk.h>
13*4882a593Smuzhiyun #include <asm/arch/gpio.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
17*4882a593Smuzhiyun * peripheral pins. Good to have if hardware is soldered optionally
18*4882a593Smuzhiyun * or in case of SPI no slave is selected. Avoid lines to float
19*4882a593Smuzhiyun * needlessly. Use a short local PUP define.
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * Due to errata "TXD floats when CTS is inactive" pullups are always
22*4882a593Smuzhiyun * on for TXD pins.
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun #ifdef CONFIG_AT91_GPIO_PULLUP
25*4882a593Smuzhiyun # define PUP CONFIG_AT91_GPIO_PULLUP
26*4882a593Smuzhiyun #else
27*4882a593Smuzhiyun # define PUP 0
28*4882a593Smuzhiyun #endif
29*4882a593Smuzhiyun
at91_serial0_hw_init(void)30*4882a593Smuzhiyun void at91_serial0_hw_init(void)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */
33*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* RXD0 */
34*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_USART0);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
at91_serial1_hw_init(void)37*4882a593Smuzhiyun void at91_serial1_hw_init(void)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
40*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 12, PUP); /* RXD1 */
41*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_USART1);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
at91_serial2_hw_init(void)44*4882a593Smuzhiyun void at91_serial2_hw_init(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
47*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 14, PUP); /* RXD2 */
48*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_USART2);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
at91_seriald_hw_init(void)51*4882a593Smuzhiyun void at91_seriald_hw_init(void)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* DRXD */
54*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
55*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_SYS);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #ifdef CONFIG_ATMEL_SPI
at91_spi0_hw_init(unsigned long cs_mask)59*4882a593Smuzhiyun void at91_spi0_hw_init(unsigned long cs_mask)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* SPI0_MISO */
62*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 26, PUP); /* SPI0_MOSI */
63*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* SPI0_SPCK */
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_SPI);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (cs_mask & (1 << 0)) {
68*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun if (cs_mask & (1 << 1)) {
71*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTB, 7, 1);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun if (cs_mask & (1 << 2)) {
74*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun if (cs_mask & (1 << 3)) {
77*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTD, 9, 1);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun if (cs_mask & (1 << 4)) {
80*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTA, 28, 1);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun if (cs_mask & (1 << 5)) {
83*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTB, 7, 1);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun if (cs_mask & (1 << 6)) {
86*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTD, 8, 1);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun if (cs_mask & (1 << 7)) {
89*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTD, 9, 1);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun #endif
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #ifdef CONFIG_GENERIC_ATMEL_MCI
at91_mci_hw_init(void)95*4882a593Smuzhiyun void at91_mci_hw_init(void)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI CLK */
98*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI CDA */
99*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI DA0 */
100*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI DA1 */
101*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI DA2 */
102*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI DA3 */
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_MCI);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun #endif
107