1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2007-2008
3*4882a593Smuzhiyun * Stelian Pop <stelian@popies.net>
4*4882a593Smuzhiyun * Lead Tech Design <www.leadtechdesign.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * (C) Copyright 2009-2011
7*4882a593Smuzhiyun * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
8*4882a593Smuzhiyun * esd electronic system design gmbh <www.esd.eu>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun #include <asm/arch/at91_common.h>
16*4882a593Smuzhiyun #include <asm/arch/clk.h>
17*4882a593Smuzhiyun #include <asm/arch/gpio.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
21*4882a593Smuzhiyun * peripheral pins. Good to have if hardware is soldered optionally
22*4882a593Smuzhiyun * or in case of SPI no slave is selected. Avoid lines to float
23*4882a593Smuzhiyun * needlessly. Use a short local PUP define.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * Due to errata "TXD floats when CTS is inactive" pullups are always
26*4882a593Smuzhiyun * on for TXD pins.
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun #ifdef CONFIG_AT91_GPIO_PULLUP
29*4882a593Smuzhiyun # define PUP CONFIG_AT91_GPIO_PULLUP
30*4882a593Smuzhiyun #else
31*4882a593Smuzhiyun # define PUP 0
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun
at91_serial0_hw_init(void)34*4882a593Smuzhiyun void at91_serial0_hw_init(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
37*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* RXD0 */
38*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_USART0);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
at91_serial1_hw_init(void)41*4882a593Smuzhiyun void at91_serial1_hw_init(void)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
44*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTD, 1, PUP); /* RXD1 */
45*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_USART1);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
at91_serial2_hw_init(void)48*4882a593Smuzhiyun void at91_serial2_hw_init(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
51*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTD, 3, PUP); /* RXD2 */
52*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_USART2);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
at91_seriald_hw_init(void)55*4882a593Smuzhiyun void at91_seriald_hw_init(void)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTC, 30, PUP); /* DRXD */
58*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
59*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_SYS);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #ifdef CONFIG_ATMEL_SPI
at91_spi0_hw_init(unsigned long cs_mask)63*4882a593Smuzhiyun void at91_spi0_hw_init(unsigned long cs_mask)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
66*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
67*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_SPI0);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun if (cs_mask & (1 << 0)) {
72*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun if (cs_mask & (1 << 1)) {
75*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun if (cs_mask & (1 << 2)) {
78*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun if (cs_mask & (1 << 3)) {
81*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun if (cs_mask & (1 << 4)) {
84*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun if (cs_mask & (1 << 5)) {
87*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun if (cs_mask & (1 << 6)) {
90*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun if (cs_mask & (1 << 7)) {
93*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
at91_spi1_hw_init(unsigned long cs_mask)97*4882a593Smuzhiyun void at91_spi1_hw_init(unsigned long cs_mask)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTB, 12, PUP); /* SPI1_MISO */
100*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTB, 13, PUP); /* SPI1_MOSI */
101*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_SPCK */
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_SPI1);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (cs_mask & (1 << 0)) {
106*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun if (cs_mask & (1 << 1)) {
109*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun if (cs_mask & (1 << 2)) {
112*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun if (cs_mask & (1 << 3)) {
115*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun if (cs_mask & (1 << 4)) {
118*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun if (cs_mask & (1 << 5)) {
121*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun if (cs_mask & (1 << 6)) {
124*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun if (cs_mask & (1 << 7)) {
127*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun #endif
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #if defined(CONFIG_GENERIC_ATMEL_MCI)
at91_mci_hw_init(void)133*4882a593Smuzhiyun void at91_mci_hw_init(void)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_MCI1);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #if defined(CONFIG_ATMEL_MCI_PORTB)
140*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */
141*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */
142*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */
143*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */
144*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */
145*4882a593Smuzhiyun #else
146*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */
147*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */
148*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */
149*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */
150*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */
151*4882a593Smuzhiyun #endif
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun #endif
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun #ifdef CONFIG_MACB
at91_macb_hw_init(void)156*4882a593Smuzhiyun void at91_macb_hw_init(void)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTE, 21, 0); /* ETXCK_EREFCK */
159*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ERXDV */
160*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTE, 25, 0); /* ERX0 */
161*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTE, 26, 0); /* ERX1 */
162*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTE, 27, 0); /* ERXER */
163*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTE, 28, 0); /* ETXEN */
164*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTE, 23, 0); /* ETX0 */
165*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTE, 24, 0); /* ETX1 */
166*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTE, 30, 0); /* EMDIO */
167*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTE, 29, 0); /* EMDC */
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun #ifndef CONFIG_RMII
170*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTE, 22, 0); /* ECRS */
171*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
172*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
173*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
174*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
175*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
176*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
177*4882a593Smuzhiyun at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
178*4882a593Smuzhiyun #endif
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun #endif
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun #ifdef CONFIG_USB_OHCI_NEW
at91_uhp_hw_init(void)183*4882a593Smuzhiyun void at91_uhp_hw_init(void)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun /* Enable VBus on UHP ports */
186*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
187*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun #endif
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun #ifdef CONFIG_AT91_CAN
at91_can_hw_init(void)192*4882a593Smuzhiyun void at91_can_hw_init(void)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */
195*4882a593Smuzhiyun at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_CAN);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun #endif
200