1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2002
3*4882a593Smuzhiyun * Lineo, Inc. <www.lineo.com>
4*4882a593Smuzhiyun * Bernhard Kuhn <bkuhn@lineo.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * (C) Copyright 2002
7*4882a593Smuzhiyun * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8*4882a593Smuzhiyun * Marius Groeger <mgroeger@sysgo.de>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * (C) Copyright 2002
11*4882a593Smuzhiyun * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
12*4882a593Smuzhiyun * Alex Zuepke <azu@sysgo.de>
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <common.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <asm/io.h>
20*4882a593Smuzhiyun #include <asm/arch/hardware.h>
21*4882a593Smuzhiyun #include <asm/arch/at91_tc.h>
22*4882a593Smuzhiyun #include <asm/arch/clk.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* the number of clocks per CONFIG_SYS_HZ */
27*4882a593Smuzhiyun #define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
28*4882a593Smuzhiyun
timer_init(void)29*4882a593Smuzhiyun int timer_init(void)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_TC0);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun writel(0, &tc->bcr);
36*4882a593Smuzhiyun writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
37*4882a593Smuzhiyun AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
40*4882a593Smuzhiyun /* set to MCLK/2 and restart the timer
41*4882a593Smuzhiyun when the value in TC_RC is reached */
42*4882a593Smuzhiyun writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
45*4882a593Smuzhiyun writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
48*4882a593Smuzhiyun gd->arch.lastinc = 0;
49*4882a593Smuzhiyun gd->arch.tbl = 0;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return 0;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * timer without interrupts
56*4882a593Smuzhiyun */
get_timer(ulong base)57*4882a593Smuzhiyun ulong get_timer(ulong base)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun return get_timer_masked() - base;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
__udelay(unsigned long usec)62*4882a593Smuzhiyun void __udelay(unsigned long usec)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun udelay_masked(usec);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
get_timer_raw(void)67*4882a593Smuzhiyun ulong get_timer_raw(void)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
70*4882a593Smuzhiyun u32 now;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun now = readl(&tc->tc[0].cv) & 0x0000ffff;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (now >= gd->arch.lastinc) {
75*4882a593Smuzhiyun /* normal mode */
76*4882a593Smuzhiyun gd->arch.tbl += now - gd->arch.lastinc;
77*4882a593Smuzhiyun } else {
78*4882a593Smuzhiyun /* we have an overflow ... */
79*4882a593Smuzhiyun gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun gd->arch.lastinc = now;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return gd->arch.tbl;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
get_timer_masked(void)86*4882a593Smuzhiyun ulong get_timer_masked(void)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun return get_timer_raw()/TIMER_LOAD_VAL;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
udelay_masked(unsigned long usec)91*4882a593Smuzhiyun void udelay_masked(unsigned long usec)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun u32 tmo;
94*4882a593Smuzhiyun u32 endtime;
95*4882a593Smuzhiyun signed long diff;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun tmo = CONFIG_SYS_HZ_CLOCK / 1000;
98*4882a593Smuzhiyun tmo *= usec;
99*4882a593Smuzhiyun tmo /= 1000;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun endtime = get_timer_raw() + tmo;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun do {
104*4882a593Smuzhiyun u32 now = get_timer_raw();
105*4882a593Smuzhiyun diff = endtime - now;
106*4882a593Smuzhiyun } while (diff >= 0);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun * This function is derived from PowerPC code (read timebase as long long).
111*4882a593Smuzhiyun * On ARM it just returns the timer value.
112*4882a593Smuzhiyun */
get_ticks(void)113*4882a593Smuzhiyun unsigned long long get_ticks(void)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun return get_timer(0);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /*
119*4882a593Smuzhiyun * This function is derived from PowerPC code (timebase clock frequency).
120*4882a593Smuzhiyun * On ARM it returns the number of timer ticks per second.
121*4882a593Smuzhiyun */
get_tbclk(void)122*4882a593Smuzhiyun ulong get_tbclk(void)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun return CONFIG_SYS_HZ;
125*4882a593Smuzhiyun }
126