1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and 3*4882a593Smuzhiyun * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Modified for the at91rm9200dk board by 6*4882a593Smuzhiyun * (C) Copyright 2004 7*4882a593Smuzhiyun * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include <config.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun#ifndef CONFIG_SKIP_LOWLEVEL_INIT 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun#include <asm/arch/hardware.h> 17*4882a593Smuzhiyun#include <asm/arch/at91_mc.h> 18*4882a593Smuzhiyun#include <asm/arch/at91_pmc.h> 19*4882a593Smuzhiyun#include <asm/arch/at91_pio.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun_MTEXT_BASE: 24*4882a593Smuzhiyun#undef START_FROM_MEM 25*4882a593Smuzhiyun#ifdef START_FROM_MEM 26*4882a593Smuzhiyun .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1 27*4882a593Smuzhiyun#else 28*4882a593Smuzhiyun .word CONFIG_SYS_TEXT_BASE 29*4882a593Smuzhiyun#endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun.globl lowlevel_init 32*4882a593Smuzhiyunlowlevel_init: 33*4882a593Smuzhiyun ldr r1, =AT91_ASM_PMC_MOR 34*4882a593Smuzhiyun /* Main oscillator Enable register */ 35*4882a593Smuzhiyun#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR 36*4882a593Smuzhiyun ldr r0, =0x0000FF01 /* Enable main oscillator */ 37*4882a593Smuzhiyun#else 38*4882a593Smuzhiyun ldr r0, =0x0000FF00 /* Disable main oscillator */ 39*4882a593Smuzhiyun#endif 40*4882a593Smuzhiyun str r0, [r1] /*AT91C_CKGR_MOR] */ 41*4882a593Smuzhiyun /* Add loop to compensate Main Oscillator startup time */ 42*4882a593Smuzhiyun ldr r0, =0x00000010 43*4882a593SmuzhiyunLoopOsc: 44*4882a593Smuzhiyun subs r0, r0, #1 45*4882a593Smuzhiyun bhi LoopOsc 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* memory control configuration */ 48*4882a593Smuzhiyun /* this isn't very elegant, but what the heck */ 49*4882a593Smuzhiyun ldr r0, =SMRDATA 50*4882a593Smuzhiyun ldr r1, _MTEXT_BASE 51*4882a593Smuzhiyun sub r0, r0, r1 52*4882a593Smuzhiyun ldr r2, =SMRDATAE 53*4882a593Smuzhiyun sub r2, r2, r1 54*4882a593Smuzhiyunpllloop: 55*4882a593Smuzhiyun /* the address */ 56*4882a593Smuzhiyun ldr r1, [r0], #4 57*4882a593Smuzhiyun /* the value */ 58*4882a593Smuzhiyun ldr r3, [r0], #4 59*4882a593Smuzhiyun str r3, [r1] 60*4882a593Smuzhiyun cmp r2, r0 61*4882a593Smuzhiyun bne pllloop 62*4882a593Smuzhiyun /* delay - this is all done by guess */ 63*4882a593Smuzhiyun ldr r0, =0x00010000 64*4882a593Smuzhiyun /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */ 65*4882a593Smuzhiyunlock: 66*4882a593Smuzhiyun subs r0, r0, #1 67*4882a593Smuzhiyun bhi lock 68*4882a593Smuzhiyun ldr r0, =SMRDATA1 69*4882a593Smuzhiyun ldr r1, _MTEXT_BASE 70*4882a593Smuzhiyun sub r0, r0, r1 71*4882a593Smuzhiyun ldr r2, =SMRDATA1E 72*4882a593Smuzhiyun sub r2, r2, r1 73*4882a593Smuzhiyunsdinit: 74*4882a593Smuzhiyun /* the address */ 75*4882a593Smuzhiyun ldr r1, [r0], #4 76*4882a593Smuzhiyun /* the value */ 77*4882a593Smuzhiyun ldr r3, [r0], #4 78*4882a593Smuzhiyun str r3, [r1] 79*4882a593Smuzhiyun cmp r2, r0 80*4882a593Smuzhiyun bne sdinit 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* switch from FastBus to Asynchronous clock mode */ 83*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 0 84*4882a593Smuzhiyun orr r0, r0, #ARM920T_CONTROL 85*4882a593Smuzhiyun mcr p15, 0, r0, c1, c0, 0 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* everything is fine now */ 88*4882a593Smuzhiyun mov pc, lr 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun .ltorg 91*4882a593Smuzhiyun 92*4882a593SmuzhiyunSMRDATA: 93*4882a593Smuzhiyun .word AT91_ASM_MC_EBI_CFG 94*4882a593Smuzhiyun .word CONFIG_SYS_EBI_CFGR_VAL 95*4882a593Smuzhiyun .word AT91_ASM_MC_SMC_CSR0 96*4882a593Smuzhiyun .word CONFIG_SYS_SMC_CSR0_VAL 97*4882a593Smuzhiyun .word AT91_ASM_PMC_PLLAR 98*4882a593Smuzhiyun .word CONFIG_SYS_PLLAR_VAL 99*4882a593Smuzhiyun .word AT91_ASM_PMC_PLLBR 100*4882a593Smuzhiyun .word CONFIG_SYS_PLLBR_VAL 101*4882a593Smuzhiyun .word AT91_ASM_PMC_MCKR 102*4882a593Smuzhiyun .word CONFIG_SYS_MCKR_VAL 103*4882a593SmuzhiyunSMRDATAE: 104*4882a593Smuzhiyun /* here there's a delay */ 105*4882a593SmuzhiyunSMRDATA1: 106*4882a593Smuzhiyun .word AT91_ASM_PIOC_ASR 107*4882a593Smuzhiyun .word CONFIG_SYS_PIOC_ASR_VAL 108*4882a593Smuzhiyun .word AT91_ASM_PIOC_BSR 109*4882a593Smuzhiyun .word CONFIG_SYS_PIOC_BSR_VAL 110*4882a593Smuzhiyun .word AT91_ASM_PIOC_PDR 111*4882a593Smuzhiyun .word CONFIG_SYS_PIOC_PDR_VAL 112*4882a593Smuzhiyun .word AT91_ASM_MC_EBI_CSA 113*4882a593Smuzhiyun .word CONFIG_SYS_EBI_CSA_VAL 114*4882a593Smuzhiyun .word AT91_ASM_MC_SDRAMC_CR 115*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_CR_VAL 116*4882a593Smuzhiyun .word AT91_ASM_MC_SDRAMC_MR 117*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_MR_VAL 118*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM 119*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 120*4882a593Smuzhiyun .word AT91_ASM_MC_SDRAMC_MR 121*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_MR_VAL1 122*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM 123*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 124*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM 125*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 126*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM 127*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 128*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM 129*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 130*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM 131*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 132*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM 133*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 134*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM 135*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 136*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM 137*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 138*4882a593Smuzhiyun .word AT91_ASM_MC_SDRAMC_MR 139*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_MR_VAL2 140*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM1 141*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 142*4882a593Smuzhiyun .word AT91_ASM_MC_SDRAMC_TR 143*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_TR_VAL 144*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM 145*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 146*4882a593Smuzhiyun .word AT91_ASM_MC_SDRAMC_MR 147*4882a593Smuzhiyun .word CONFIG_SYS_SDRC_MR_VAL3 148*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM 149*4882a593Smuzhiyun .word CONFIG_SYS_SDRAM_VAL 150*4882a593SmuzhiyunSMRDATA1E: 151*4882a593Smuzhiyun /* SMRDATA1 is 176 bytes long */ 152*4882a593Smuzhiyun#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 153