1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #include <common.h> 7*4882a593Smuzhiyun #include <dm.h> 8*4882a593Smuzhiyun #include <ram.h> 9*4882a593Smuzhiyun #include <timer.h> 10*4882a593Smuzhiyun #include <asm/io.h> 11*4882a593Smuzhiyun #include <asm/arch/timer.h> 12*4882a593Smuzhiyun #include <asm/arch/wdt.h> 13*4882a593Smuzhiyun #include <linux/err.h> 14*4882a593Smuzhiyun #include <dm/uclass.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Second Watchdog Timer by default is configured 18*4882a593Smuzhiyun * to trigger secondary boot source. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define AST_2ND_BOOT_WDT 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * Third Watchdog Timer by default is configured 24*4882a593Smuzhiyun * to toggle Flash address mode switch before reset. 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define AST_FLASH_ADDR_DETECT_WDT 2 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 29*4882a593Smuzhiyun lowlevel_init(void)30*4882a593Smuzhiyunvoid lowlevel_init(void) 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * These two watchdogs need to be stopped as soon as possible, 34*4882a593Smuzhiyun * otherwise the board might hang. By default they are set to 35*4882a593Smuzhiyun * a very short timeout and even simple debug write to serial 36*4882a593Smuzhiyun * console early in the init process might cause them to fire. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun struct ast_wdt *flash_addr_wdt = 39*4882a593Smuzhiyun (struct ast_wdt *)(WDT_BASE + 40*4882a593Smuzhiyun sizeof(struct ast_wdt) * 41*4882a593Smuzhiyun AST_FLASH_ADDR_DETECT_WDT); 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #ifndef CONFIG_FIRMWARE_2ND_BOOT 46*4882a593Smuzhiyun struct ast_wdt *sec_boot_wdt = 47*4882a593Smuzhiyun (struct ast_wdt *)(WDT_BASE + 48*4882a593Smuzhiyun sizeof(struct ast_wdt) * 49*4882a593Smuzhiyun AST_2ND_BOOT_WDT); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN); 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun } 54*4882a593Smuzhiyun board_init(void)55*4882a593Smuzhiyunint board_init(void) 56*4882a593Smuzhiyun { 57*4882a593Smuzhiyun gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun return 0; 60*4882a593Smuzhiyun } 61*4882a593Smuzhiyun dram_init(void)62*4882a593Smuzhiyunint dram_init(void) 63*4882a593Smuzhiyun { 64*4882a593Smuzhiyun struct udevice *dev; 65*4882a593Smuzhiyun struct ram_info ram; 66*4882a593Smuzhiyun int ret; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun ret = uclass_get_device(UCLASS_RAM, 0, &dev); 69*4882a593Smuzhiyun if (ret) { 70*4882a593Smuzhiyun debug("DRAM FAIL1\r\n"); 71*4882a593Smuzhiyun return ret; 72*4882a593Smuzhiyun } 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun ret = ram_get_info(dev, &ram); 75*4882a593Smuzhiyun if (ret) { 76*4882a593Smuzhiyun debug("DRAM FAIL2\r\n"); 77*4882a593Smuzhiyun return ret; 78*4882a593Smuzhiyun } 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun gd->ram_size = ram.size; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun return 0; 83*4882a593Smuzhiyun } 84