1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2015 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Extracted from gic_64.S 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <config.h> 10*4882a593Smuzhiyun#include <linux/linkage.h> 11*4882a593Smuzhiyun#include <asm/macro.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/************************************************************************* 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST, 16*4882a593Smuzhiyun * CCI_MN_DVM_DOMAIN_CTL_SET); 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * Add fully-coherent masters to DVM domain 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun *************************************************************************/ 21*4882a593SmuzhiyunENTRY(ccn504_add_masters_to_dvm) 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * x0: CCI_MN_BASE 24*4882a593Smuzhiyun * x1: CCI_MN_RNF_NODEID_LIST 25*4882a593Smuzhiyun * x2: CCI_MN_DVM_DOMAIN_CTL_SET 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Add fully-coherent masters to DVM domain */ 29*4882a593Smuzhiyun ldr x9, [x0, x1] 30*4882a593Smuzhiyun str x9, [x0, x2] 31*4882a593Smuzhiyun1: ldr x10, [x0, x2] 32*4882a593Smuzhiyun mvn x11, x10 33*4882a593Smuzhiyun tst x11, x10 /* Wait for domain addition to complete */ 34*4882a593Smuzhiyun b.ne 1b 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun ret 37*4882a593SmuzhiyunENDPROC(ccn504_add_masters_to_dvm) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun/************************************************************************* 40*4882a593Smuzhiyun * 41*4882a593Smuzhiyun * void ccn504_set_qos(CCI_Sx_QOS_CONTROL_BASE, QoS Value); 42*4882a593Smuzhiyun * 43*4882a593Smuzhiyun * Initialize QoS settings for AR/AW override. 44*4882a593Smuzhiyun * Right now, this function sets the same QoS value for all RN-I ports 45*4882a593Smuzhiyun * 46*4882a593Smuzhiyun *************************************************************************/ 47*4882a593SmuzhiyunENTRY(ccn504_set_qos) 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * x0: CCI_Sx_QOS_CONTROL_BASE 50*4882a593Smuzhiyun * x1: QoS Value 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Set all RN-I ports to QoS value denoted by x1 */ 54*4882a593Smuzhiyun ldr x9, [x0] 55*4882a593Smuzhiyun mov x10, x1 56*4882a593Smuzhiyun orr x9, x9, x10 57*4882a593Smuzhiyun str x9, [x0] 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun ret 60*4882a593SmuzhiyunENDPROC(ccn504_set_qos) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun/************************************************************************* 63*4882a593Smuzhiyun * 64*4882a593Smuzhiyun * void ccn504_set_aux(CCI_AUX_CONTROL_BASE, Value); 65*4882a593Smuzhiyun * 66*4882a593Smuzhiyun * Initialize AUX control settings 67*4882a593Smuzhiyun * 68*4882a593Smuzhiyun *************************************************************************/ 69*4882a593SmuzhiyunENTRY(ccn504_set_aux) 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * x0: CCI_AUX_CONTROL_BASE 72*4882a593Smuzhiyun * x1: Value 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun ldr x9, [x0] 76*4882a593Smuzhiyun mov x10, x1 77*4882a593Smuzhiyun orr x9, x9, x10 78*4882a593Smuzhiyun str x9, [x0] 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun ret 81*4882a593SmuzhiyunENDPROC(ccn504_set_aux) 82*4882a593Smuzhiyun 83