1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _PL310_H_ 9*4882a593Smuzhiyun #define _PL310_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/types.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Register bit fields */ 14*4882a593Smuzhiyun #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) 15*4882a593Smuzhiyun #define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) 16*4882a593Smuzhiyun #define L2X0_STNDBY_MODE_EN (1 << 0) 17*4882a593Smuzhiyun #define L2X0_CTRL_EN 1 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) 20*4882a593Smuzhiyun #define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) 21*4882a593Smuzhiyun #define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct pl310_regs { 24*4882a593Smuzhiyun u32 pl310_cache_id; 25*4882a593Smuzhiyun u32 pl310_cache_type; 26*4882a593Smuzhiyun u32 pad1[62]; 27*4882a593Smuzhiyun u32 pl310_ctrl; 28*4882a593Smuzhiyun u32 pl310_aux_ctrl; 29*4882a593Smuzhiyun u32 pl310_tag_latency_ctrl; 30*4882a593Smuzhiyun u32 pl310_data_latency_ctrl; 31*4882a593Smuzhiyun u32 pad2[60]; 32*4882a593Smuzhiyun u32 pl310_event_cnt_ctrl; 33*4882a593Smuzhiyun u32 pl310_event_cnt1_cfg; 34*4882a593Smuzhiyun u32 pl310_event_cnt0_cfg; 35*4882a593Smuzhiyun u32 pl310_event_cnt1_val; 36*4882a593Smuzhiyun u32 pl310_event_cnt0_val; 37*4882a593Smuzhiyun u32 pl310_intr_mask; 38*4882a593Smuzhiyun u32 pl310_masked_intr_stat; 39*4882a593Smuzhiyun u32 pl310_raw_intr_stat; 40*4882a593Smuzhiyun u32 pl310_intr_clear; 41*4882a593Smuzhiyun u32 pad3[323]; 42*4882a593Smuzhiyun u32 pl310_cache_sync; 43*4882a593Smuzhiyun u32 pad4[15]; 44*4882a593Smuzhiyun u32 pl310_inv_line_pa; 45*4882a593Smuzhiyun u32 pad5[2]; 46*4882a593Smuzhiyun u32 pl310_inv_way; 47*4882a593Smuzhiyun u32 pad6[12]; 48*4882a593Smuzhiyun u32 pl310_clean_line_pa; 49*4882a593Smuzhiyun u32 pad7[1]; 50*4882a593Smuzhiyun u32 pl310_clean_line_idx; 51*4882a593Smuzhiyun u32 pl310_clean_way; 52*4882a593Smuzhiyun u32 pad8[12]; 53*4882a593Smuzhiyun u32 pl310_clean_inv_line_pa; 54*4882a593Smuzhiyun u32 pad9[1]; 55*4882a593Smuzhiyun u32 pl310_clean_inv_line_idx; 56*4882a593Smuzhiyun u32 pl310_clean_inv_way; 57*4882a593Smuzhiyun u32 pad10[64]; 58*4882a593Smuzhiyun u32 pl310_lockdown_dbase; 59*4882a593Smuzhiyun u32 pl310_lockdown_ibase; 60*4882a593Smuzhiyun u32 pad11[190]; 61*4882a593Smuzhiyun u32 pl310_addr_filter_start; 62*4882a593Smuzhiyun u32 pl310_addr_filter_end; 63*4882a593Smuzhiyun u32 pad12[190]; 64*4882a593Smuzhiyun u32 pl310_test_operation; 65*4882a593Smuzhiyun u32 pad13[3]; 66*4882a593Smuzhiyun u32 pl310_line_data; 67*4882a593Smuzhiyun u32 pad14[7]; 68*4882a593Smuzhiyun u32 pl310_line_tag; 69*4882a593Smuzhiyun u32 pad15[3]; 70*4882a593Smuzhiyun u32 pl310_debug_ctrl; 71*4882a593Smuzhiyun u32 pad16[7]; 72*4882a593Smuzhiyun u32 pl310_prefetch_ctrl; 73*4882a593Smuzhiyun u32 pad17[7]; 74*4882a593Smuzhiyun u32 pl310_power_ctrl; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun void pl310_inval_all(void); 78*4882a593Smuzhiyun void pl310_clean_inval_all(void); 79*4882a593Smuzhiyun void pl310_inval_range(u32 start, u32 end); 80*4882a593Smuzhiyun void pl310_clean_inval_range(u32 start, u32 end); 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif 83