1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2009
3*4882a593Smuzhiyun * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _SYS_PROTO_H_
9*4882a593Smuzhiyun #define _SYS_PROTO_H_
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/mach-imx/regs-common.h>
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun #include "../arch-imx/cpu.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define soc_rev() (get_cpu_rev() & 0xFF)
17*4882a593Smuzhiyun #define is_soc_rev(rev) (soc_rev() == rev)
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* returns MXC_CPU_ value */
20*4882a593Smuzhiyun #define cpu_type(rev) (((rev) >> 12) & 0xff)
21*4882a593Smuzhiyun #define soc_type(rev) (((rev) >> 12) & 0xf0)
22*4882a593Smuzhiyun /* both macros return/take MXC_CPU_ constants */
23*4882a593Smuzhiyun #define get_cpu_type() (cpu_type(get_cpu_rev()))
24*4882a593Smuzhiyun #define get_soc_type() (soc_type(get_cpu_rev()))
25*4882a593Smuzhiyun #define is_cpu_type(cpu) (get_cpu_type() == cpu)
26*4882a593Smuzhiyun #define is_soc_type(soc) (get_soc_type() == soc)
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define is_mx6() (is_soc_type(MXC_SOC_MX6))
29*4882a593Smuzhiyun #define is_mx7() (is_soc_type(MXC_SOC_MX7))
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
32*4882a593Smuzhiyun #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
33*4882a593Smuzhiyun #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
34*4882a593Smuzhiyun #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
35*4882a593Smuzhiyun #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
36*4882a593Smuzhiyun #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
37*4882a593Smuzhiyun #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
38*4882a593Smuzhiyun #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
39*4882a593Smuzhiyun #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
40*4882a593Smuzhiyun #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #ifdef CONFIG_MX6
45*4882a593Smuzhiyun #define IMX6_SRC_GPR10_BMODE BIT(28)
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define IMX6_BMODE_MASK GENMASK(7, 0)
48*4882a593Smuzhiyun #define IMX6_BMODE_SHIFT 4
49*4882a593Smuzhiyun #define IMX6_BMODE_EMI_MASK BIT(3)
50*4882a593Smuzhiyun #define IMX6_BMODE_EMI_SHIFT 3
51*4882a593Smuzhiyun #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
52*4882a593Smuzhiyun #define IMX6_BMODE_SERIAL_ROM_SHIFT 24
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun enum imx6_bmode_serial_rom {
55*4882a593Smuzhiyun IMX6_BMODE_ECSPI1,
56*4882a593Smuzhiyun IMX6_BMODE_ECSPI2,
57*4882a593Smuzhiyun IMX6_BMODE_ECSPI3,
58*4882a593Smuzhiyun IMX6_BMODE_ECSPI4,
59*4882a593Smuzhiyun IMX6_BMODE_ECSPI5,
60*4882a593Smuzhiyun IMX6_BMODE_I2C1,
61*4882a593Smuzhiyun IMX6_BMODE_I2C2,
62*4882a593Smuzhiyun IMX6_BMODE_I2C3,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun enum imx6_bmode_emi {
66*4882a593Smuzhiyun IMX6_BMODE_ONENAND,
67*4882a593Smuzhiyun IMX6_BMODE_NOR,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun enum imx6_bmode {
71*4882a593Smuzhiyun IMX6_BMODE_EMI,
72*4882a593Smuzhiyun #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
73*4882a593Smuzhiyun IMX6_BMODE_QSPI,
74*4882a593Smuzhiyun IMX6_BMODE_RESERVED,
75*4882a593Smuzhiyun #else
76*4882a593Smuzhiyun IMX6_BMODE_RESERVED,
77*4882a593Smuzhiyun IMX6_BMODE_SATA,
78*4882a593Smuzhiyun #endif
79*4882a593Smuzhiyun IMX6_BMODE_SERIAL_ROM,
80*4882a593Smuzhiyun IMX6_BMODE_SD,
81*4882a593Smuzhiyun IMX6_BMODE_ESD,
82*4882a593Smuzhiyun IMX6_BMODE_MMC,
83*4882a593Smuzhiyun IMX6_BMODE_EMMC,
84*4882a593Smuzhiyun IMX6_BMODE_NAND,
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
imx6_is_bmode_from_gpr9(void)87*4882a593Smuzhiyun static inline u8 imx6_is_bmode_from_gpr9(void)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun u32 imx6_src_get_boot_mode(void);
93*4882a593Smuzhiyun void gpr_init(void);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #endif /* CONFIG_MX6 */
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun u32 get_nr_cpus(void);
98*4882a593Smuzhiyun u32 get_cpu_rev(void);
99*4882a593Smuzhiyun u32 get_cpu_speed_grade_hz(void);
100*4882a593Smuzhiyun u32 get_cpu_temp_grade(int *minc, int *maxc);
101*4882a593Smuzhiyun const char *get_imx_type(u32 imxtype);
102*4882a593Smuzhiyun u32 imx_ddr_size(void);
103*4882a593Smuzhiyun void sdelay(unsigned long);
104*4882a593Smuzhiyun void set_chipselect_size(int const);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun void init_aips(void);
107*4882a593Smuzhiyun void init_src(void);
108*4882a593Smuzhiyun void imx_set_wdog_powerdown(bool enable);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /*
111*4882a593Smuzhiyun * Initializes on-chip ethernet controllers.
112*4882a593Smuzhiyun * to override, implement board_eth_init()
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun int fecmxc_initialize(bd_t *bis);
115*4882a593Smuzhiyun u32 get_ahb_clk(void);
116*4882a593Smuzhiyun u32 get_periph_clk(void);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun void lcdif_power_down(void);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun int mxs_reset_block(struct mxs_register_32 *reg);
121*4882a593Smuzhiyun int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
122*4882a593Smuzhiyun int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
123*4882a593Smuzhiyun #endif
124