1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __RDC_SEMA_H__ 8*4882a593Smuzhiyun #define __RDC_SEMA_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * rdc_peri_cfg_t and rdc_ma_cft_t use the same layout. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ] 14*4882a593Smuzhiyun * d3 d2 d1 d0 | master id | peri id 15*4882a593Smuzhiyun * d[x] means domain[x], x can be [3 - 0]. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun typedef u32 rdc_peri_cfg_t; 18*4882a593Smuzhiyun typedef u32 rdc_ma_cfg_t; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define RDC_PERI_SHIFT 0 21*4882a593Smuzhiyun #define RDC_PERI_MASK 0xFF 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define RDC_DOMAIN_SHIFT_BASE 16 24*4882a593Smuzhiyun #define RDC_DOMAIN_MASK 0xFF0000 25*4882a593Smuzhiyun #define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1))) 26*4882a593Smuzhiyun #define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x))) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define RDC_MASTER_SHIFT 8 29*4882a593Smuzhiyun #define RDC_MASTER_MASK 0xFF00 30*4882a593Smuzhiyun #define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \ 31*4882a593Smuzhiyun (domain_id << RDC_DOMAIN_SHIFT_BASE)) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* The Following macro definitions are common to i.MX6SX and i.MX7D */ 34*4882a593Smuzhiyun #define SEMA_GATES_NUM 64 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define RDC_MDA_DID_SHIFT 0 37*4882a593Smuzhiyun #define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT) 38*4882a593Smuzhiyun #define RDC_MDA_LCK_SHIFT 31 39*4882a593Smuzhiyun #define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1) 42*4882a593Smuzhiyun #define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain)) 43*4882a593Smuzhiyun #define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain)) 44*4882a593Smuzhiyun #define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain)) 45*4882a593Smuzhiyun #define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \ 46*4882a593Smuzhiyun RDC_PDAP_DR_MASK(domain)) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define RDC_PDAP_SREQ_SHIFT 30 49*4882a593Smuzhiyun #define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT) 50*4882a593Smuzhiyun #define RDC_PDAP_LCK_SHIFT 31 51*4882a593Smuzhiyun #define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define RDC_MRSA_SADR_SHIFT 7 54*4882a593Smuzhiyun #define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define RDC_MREA_EADR_SHIFT 7 57*4882a593Smuzhiyun #define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define RDC_MRC_DW_SHIFT(domain) (domain) 60*4882a593Smuzhiyun #define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain)) 61*4882a593Smuzhiyun #define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain)) 62*4882a593Smuzhiyun #define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain)) 63*4882a593Smuzhiyun #define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \ 64*4882a593Smuzhiyun RDC_MRC_DR_MASK(domain)) 65*4882a593Smuzhiyun #define RDC_MRC_ENA_SHIFT 30 66*4882a593Smuzhiyun #define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT) 67*4882a593Smuzhiyun #define RDC_MRC_LCK_SHIFT 31 68*4882a593Smuzhiyun #define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define RDC_MRVS_VDID_SHIFT 0 71*4882a593Smuzhiyun #define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT) 72*4882a593Smuzhiyun #define RDC_MRVS_AD_SHIFT 4 73*4882a593Smuzhiyun #define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT) 74*4882a593Smuzhiyun #define RDC_MRVS_VADDR_SHIFT 5 75*4882a593Smuzhiyun #define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define RDC_SEMA_GATE_GTFSM_SHIFT 0 78*4882a593Smuzhiyun #define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT) 79*4882a593Smuzhiyun #define RDC_SEMA_GATE_LDOM_SHIFT 5 80*4882a593Smuzhiyun #define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0 83*4882a593Smuzhiyun #define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT) 84*4882a593Smuzhiyun #define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2 85*4882a593Smuzhiyun #define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT) 86*4882a593Smuzhiyun #define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4 87*4882a593Smuzhiyun #define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT) 88*4882a593Smuzhiyun #define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8 89*4882a593Smuzhiyun #define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun int imx_rdc_check_permission(int per_id, int dom_id); 92*4882a593Smuzhiyun int imx_rdc_sema_lock(int per_id); 93*4882a593Smuzhiyun int imx_rdc_sema_unlock(int per_id); 94*4882a593Smuzhiyun int imx_rdc_setup_peri(rdc_peri_cfg_t p); 95*4882a593Smuzhiyun int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list, 96*4882a593Smuzhiyun unsigned count); 97*4882a593Smuzhiyun int imx_rdc_setup_ma(rdc_ma_cfg_t p); 98*4882a593Smuzhiyun int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count); 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #endif /* __RDC_SEMA_H__*/ 101