1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __FSL_SECURE_BOOT_H 8*4882a593Smuzhiyun #define __FSL_SECURE_BOOT_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifdef CONFIG_CHAIN_OF_TRUST 11*4882a593Smuzhiyun #define CONFIG_FSL_SEC_MON 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Define the key hash for U-Boot here if public/private key pair used to 16*4882a593Smuzhiyun * sign U-boot are different from the SRK hash put in the fuse 17*4882a593Smuzhiyun * Example of defining KEY_HASH is 18*4882a593Smuzhiyun * #define CONFIG_SPL_UBOOT_KEY_HASH \ 19*4882a593Smuzhiyun * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 20*4882a593Smuzhiyun * else leave it defined as NULL 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CONFIG_SPL_UBOOT_KEY_HASH NULL 24*4882a593Smuzhiyun #endif /* ifdef CONFIG_SPL_BUILD */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CONFIG_KEY_REVOCATION 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 29*4882a593Smuzhiyun #ifndef CONFIG_SYS_RAMBOOT 30*4882a593Smuzhiyun /* The key used for verification of next level images 31*4882a593Smuzhiyun * is picked up from an Extension Table which has 32*4882a593Smuzhiyun * been verified by the ISBC (Internal Secure boot Code) 33*4882a593Smuzhiyun * in boot ROM of the SoC. 34*4882a593Smuzhiyun * The feature is only applicable in case of NOR boot and is 35*4882a593Smuzhiyun * not applicable in case of RAMBOOT (NAND, SD, SPI). 36*4882a593Smuzhiyun * For LS, this feature is available for all device if IE Table 37*4882a593Smuzhiyun * is copied to XIP memory 38*4882a593Smuzhiyun * Also, for LS, ISBC doesn't verify this table. 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define CONFIG_FSL_ISBC_KEY_EXT 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #endif 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #if defined(CONFIG_FSL_LAYERSCAPE) 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * For fsl layerscape based platforms, ESBC image Address in Header 47*4882a593Smuzhiyun * is 64 bit. 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define CONFIG_ESBC_ADDR_64BIT 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #ifdef CONFIG_ARCH_LS2080A 53*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV \ 54*4882a593Smuzhiyun "setenv fdt_high 0xa0000000;" \ 55*4882a593Smuzhiyun "setenv initrd_high 0xcfffffff;" \ 56*4882a593Smuzhiyun "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 57*4882a593Smuzhiyun #else 58*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV \ 59*4882a593Smuzhiyun "setenv fdt_high 0xffffffff;" \ 60*4882a593Smuzhiyun "setenv initrd_high 0xffffffff;" \ 61*4882a593Smuzhiyun "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 62*4882a593Smuzhiyun #endif 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from 65*4882a593Smuzhiyun * Non-XIP Memory (Nand/SD)*/ 66*4882a593Smuzhiyun #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ 67*4882a593Smuzhiyun defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT) 68*4882a593Smuzhiyun #define CONFIG_BOOTSCRIPT_COPY_RAM 69*4882a593Smuzhiyun #endif 70*4882a593Smuzhiyun /* The address needs to be modified according to NOR, NAND, SD and 71*4882a593Smuzhiyun * DDR memory map 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun #ifdef CONFIG_FSL_LSCH3 74*4882a593Smuzhiyun #define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000 75*4882a593Smuzhiyun #define CONFIG_BS_ADDR_DEVICE 0x580e00000 76*4882a593Smuzhiyun #define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000 77*4882a593Smuzhiyun #define CONFIG_BS_ADDR_RAM 0xa0e00000 78*4882a593Smuzhiyun #define CONFIG_BS_HDR_SIZE 0x00002000 79*4882a593Smuzhiyun #define CONFIG_BS_SIZE 0x00001000 80*4882a593Smuzhiyun #else 81*4882a593Smuzhiyun #ifdef CONFIG_SD_BOOT 82*4882a593Smuzhiyun /* For SD boot address and size are assigned in terms of sector 83*4882a593Smuzhiyun * offset and no. of sectors respectively. 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 86*4882a593Smuzhiyun #define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920 87*4882a593Smuzhiyun #else 88*4882a593Smuzhiyun #define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900 89*4882a593Smuzhiyun #endif 90*4882a593Smuzhiyun #define CONFIG_BS_ADDR_DEVICE 0x00000940 91*4882a593Smuzhiyun #define CONFIG_BS_HDR_SIZE 0x00000010 92*4882a593Smuzhiyun #define CONFIG_BS_SIZE 0x00000008 93*4882a593Smuzhiyun #elif defined(CONFIG_NAND_BOOT) 94*4882a593Smuzhiyun #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 95*4882a593Smuzhiyun #define CONFIG_BS_ADDR_DEVICE 0x00802000 96*4882a593Smuzhiyun #define CONFIG_BS_HDR_SIZE 0x00002000 97*4882a593Smuzhiyun #define CONFIG_BS_SIZE 0x00001000 98*4882a593Smuzhiyun #elif defined(CONFIG_QSPI_BOOT) 99*4882a593Smuzhiyun #ifdef CONFIG_ARCH_LS1046A 100*4882a593Smuzhiyun #define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000 101*4882a593Smuzhiyun #define CONFIG_BS_ADDR_DEVICE 0x40800000 102*4882a593Smuzhiyun #elif defined(CONFIG_ARCH_LS1012A) 103*4882a593Smuzhiyun #define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000 104*4882a593Smuzhiyun #define CONFIG_BS_ADDR_DEVICE 0x40060000 105*4882a593Smuzhiyun #else 106*4882a593Smuzhiyun #error "Platform not supported" 107*4882a593Smuzhiyun #endif 108*4882a593Smuzhiyun #define CONFIG_BS_HDR_SIZE 0x00002000 109*4882a593Smuzhiyun #define CONFIG_BS_SIZE 0x00001000 110*4882a593Smuzhiyun #else /* Default NOR Boot */ 111*4882a593Smuzhiyun #define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 112*4882a593Smuzhiyun #define CONFIG_BS_ADDR_DEVICE 0x60060000 113*4882a593Smuzhiyun #define CONFIG_BS_HDR_SIZE 0x00002000 114*4882a593Smuzhiyun #define CONFIG_BS_SIZE 0x00001000 115*4882a593Smuzhiyun #endif 116*4882a593Smuzhiyun #define CONFIG_BS_HDR_ADDR_RAM 0x81000000 117*4882a593Smuzhiyun #define CONFIG_BS_ADDR_RAM 0x81020000 118*4882a593Smuzhiyun #endif 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 121*4882a593Smuzhiyun #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 122*4882a593Smuzhiyun #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM 123*4882a593Smuzhiyun #else 124*4882a593Smuzhiyun #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE 125*4882a593Smuzhiyun /* BOOTSCRIPT_ADDR is not required */ 126*4882a593Smuzhiyun #endif 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #ifdef CONFIG_FSL_LS_PPA 129*4882a593Smuzhiyun /* Define the key hash here if SRK used for signing PPA image is 130*4882a593Smuzhiyun * different from SRK hash put in SFP used for U-Boot. 131*4882a593Smuzhiyun * Example 132*4882a593Smuzhiyun * #define PPA_KEY_HASH \ 133*4882a593Smuzhiyun * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 134*4882a593Smuzhiyun */ 135*4882a593Smuzhiyun #define PPA_KEY_HASH NULL 136*4882a593Smuzhiyun #endif /* ifdef CONFIG_FSL_LS_PPA */ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #include <config_fsl_chain_trust.h> 139*4882a593Smuzhiyun #endif /* #ifndef CONFIG_SPL_BUILD */ 140*4882a593Smuzhiyun #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 141*4882a593Smuzhiyun #endif 142