1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 4*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ASM_CACHE_H 10*4882a593Smuzhiyun #define _ASM_CACHE_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/system.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef CONFIG_ARM64 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Invalidate L2 Cache using co-proc instruction 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) 20*4882a593Smuzhiyun void invalidate_l2_cache(void); 21*4882a593Smuzhiyun #else invalidate_l2_cache(void)22*4882a593Smuzhiyunstatic inline void invalidate_l2_cache(void) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun unsigned int val=0; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" 27*4882a593Smuzhiyun : : "r" (val) : "cc"); 28*4882a593Smuzhiyun isb(); 29*4882a593Smuzhiyun } 30*4882a593Smuzhiyun #endif 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun int check_cache_range(unsigned long start, unsigned long stop); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun void l2_cache_enable(void); 35*4882a593Smuzhiyun void l2_cache_disable(void); 36*4882a593Smuzhiyun void set_section_dcache(int section, enum dcache_option option); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun void arm_init_before_mmu(void); 39*4882a593Smuzhiyun void arm_init_domains(void); 40*4882a593Smuzhiyun void cpu_cache_initialization(void); 41*4882a593Smuzhiyun void dram_bank_mmu_setup(int bank); 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #endif 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * The value of the largest data cache relevant to DMA operations shall be set 47*4882a593Smuzhiyun * for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger 48*4882a593Smuzhiyun * value than found in the L1 cache but this is OK to use in terms of 49*4882a593Smuzhiyun * alignment. 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif /* _ASM_CACHE_H */ 54