1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 ARM Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * ARM and ARM64 barrier instructions 5*4882a593Smuzhiyun * split from armv7.h to allow sharing between ARM and ARM64 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Original copyright in armv7.h was: 8*4882a593Smuzhiyun * (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Much of the original barrier code was contributed by: 11*4882a593Smuzhiyun * Valentine Barshak <valentine.barshak@cogentembedded.com> 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #ifndef __BARRIERS_H__ 16*4882a593Smuzhiyun #define __BARRIERS_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #ifndef CONFIG_ARM64 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * CP15 Barrier instructions 23*4882a593Smuzhiyun * Please note that we have separate barrier instructions in ARMv7 24*4882a593Smuzhiyun * However, we use the CP15 based instructtions because we use 25*4882a593Smuzhiyun * -march=armv5 in U-Boot 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) 28*4882a593Smuzhiyun #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) 29*4882a593Smuzhiyun #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif /* !CONFIG_ARM64 */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #if __LINUX_ARM_ARCH__ >= 7 34*4882a593Smuzhiyun #define ISB asm volatile ("isb sy" : : : "memory") 35*4882a593Smuzhiyun #define DSB asm volatile ("dsb sy" : : : "memory") 36*4882a593Smuzhiyun #define DMB asm volatile ("dmb sy" : : : "memory") 37*4882a593Smuzhiyun #elif __LINUX_ARM_ARCH__ == 6 38*4882a593Smuzhiyun #define ISB CP15ISB 39*4882a593Smuzhiyun #define DSB CP15DSB 40*4882a593Smuzhiyun #define DMB CP15DMB 41*4882a593Smuzhiyun #else 42*4882a593Smuzhiyun #define ISB asm volatile ("" : : : "memory") 43*4882a593Smuzhiyun #define DSB CP15DSB 44*4882a593Smuzhiyun #define DMB asm volatile ("" : : : "memory") 45*4882a593Smuzhiyun #endif 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define isb() ISB 48*4882a593Smuzhiyun #define dsb() DSB 49*4882a593Smuzhiyun #define dmb() DMB 50*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 51*4882a593Smuzhiyun #endif /* __BARRIERS_H__ */ 52