1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2013
3*4882a593Smuzhiyun * David Feng <fenghua@phytium.com.cn>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _ASM_ARMV8_MMU_H_
9*4882a593Smuzhiyun #define _ASM_ARMV8_MMU_H_
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /*
12*4882a593Smuzhiyun * block/section address mask and size definitions.
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* PAGE_SHIFT determines the page size */
16*4882a593Smuzhiyun #undef PAGE_SIZE
17*4882a593Smuzhiyun #define PAGE_SHIFT 12
18*4882a593Smuzhiyun #define PAGE_SIZE (1 << PAGE_SHIFT)
19*4882a593Smuzhiyun #define PAGE_MASK (~(PAGE_SIZE - 1))
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /***************************************************************/
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * Memory types
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun #define MT_DEVICE_NGNRNE 0
27*4882a593Smuzhiyun #define MT_DEVICE_NGNRE 1
28*4882a593Smuzhiyun #define MT_DEVICE_GRE 2
29*4882a593Smuzhiyun #define MT_NORMAL_NC 3
30*4882a593Smuzhiyun #define MT_NORMAL 4
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
33*4882a593Smuzhiyun (0x04 << (MT_DEVICE_NGNRE * 8)) | \
34*4882a593Smuzhiyun (0x0c << (MT_DEVICE_GRE * 8)) | \
35*4882a593Smuzhiyun (0x44 << (MT_NORMAL_NC * 8)) | \
36*4882a593Smuzhiyun (UL(0xff) << (MT_NORMAL * 8)))
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * Hardware page table definitions.
40*4882a593Smuzhiyun *
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define PTE_TYPE_MASK (3 << 0)
44*4882a593Smuzhiyun #define PTE_TYPE_FAULT (0 << 0)
45*4882a593Smuzhiyun #define PTE_TYPE_TABLE (3 << 0)
46*4882a593Smuzhiyun #define PTE_TYPE_PAGE (3 << 0)
47*4882a593Smuzhiyun #define PTE_TYPE_BLOCK (1 << 0)
48*4882a593Smuzhiyun #define PTE_TYPE_VALID (1 << 0)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define PTE_TABLE_PXN (1UL << 59)
51*4882a593Smuzhiyun #define PTE_TABLE_XN (1UL << 60)
52*4882a593Smuzhiyun #define PTE_TABLE_AP (1UL << 61)
53*4882a593Smuzhiyun #define PTE_TABLE_NS (1UL << 63)
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * Block
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun #define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
59*4882a593Smuzhiyun #define PTE_BLOCK_NS (1 << 5)
60*4882a593Smuzhiyun #define PTE_BLOCK_NON_SHARE (0 << 8)
61*4882a593Smuzhiyun #define PTE_BLOCK_OUTER_SHARE (2 << 8)
62*4882a593Smuzhiyun #define PTE_BLOCK_INNER_SHARE (3 << 8)
63*4882a593Smuzhiyun #define PTE_BLOCK_AF (1 << 10)
64*4882a593Smuzhiyun #define PTE_BLOCK_NG (1 << 11)
65*4882a593Smuzhiyun #define PTE_BLOCK_PXN (UL(1) << 53)
66*4882a593Smuzhiyun #define PTE_BLOCK_UXN (UL(1) << 54)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /*
69*4882a593Smuzhiyun * AttrIndx[2:0]
70*4882a593Smuzhiyun */
71*4882a593Smuzhiyun #define PMD_ATTRINDX(t) ((t) << 2)
72*4882a593Smuzhiyun #define PMD_ATTRINDX_MASK (7 << 2)
73*4882a593Smuzhiyun #define PMD_ATTRMASK (PTE_BLOCK_PXN | \
74*4882a593Smuzhiyun PTE_BLOCK_UXN | \
75*4882a593Smuzhiyun PMD_ATTRINDX_MASK | \
76*4882a593Smuzhiyun PTE_TYPE_VALID)
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /*
79*4882a593Smuzhiyun * TCR flags.
80*4882a593Smuzhiyun */
81*4882a593Smuzhiyun #define TCR_T0SZ(x) ((64 - (x)) << 0)
82*4882a593Smuzhiyun #define TCR_IRGN_NC (0 << 8)
83*4882a593Smuzhiyun #define TCR_IRGN_WBWA (1 << 8)
84*4882a593Smuzhiyun #define TCR_IRGN_WT (2 << 8)
85*4882a593Smuzhiyun #define TCR_IRGN_WBNWA (3 << 8)
86*4882a593Smuzhiyun #define TCR_IRGN_MASK (3 << 8)
87*4882a593Smuzhiyun #define TCR_ORGN_NC (0 << 10)
88*4882a593Smuzhiyun #define TCR_ORGN_WBWA (1 << 10)
89*4882a593Smuzhiyun #define TCR_ORGN_WT (2 << 10)
90*4882a593Smuzhiyun #define TCR_ORGN_WBNWA (3 << 10)
91*4882a593Smuzhiyun #define TCR_ORGN_MASK (3 << 10)
92*4882a593Smuzhiyun #define TCR_SHARED_NON (0 << 12)
93*4882a593Smuzhiyun #define TCR_SHARED_OUTER (2 << 12)
94*4882a593Smuzhiyun #define TCR_SHARED_INNER (3 << 12)
95*4882a593Smuzhiyun #define TCR_TG0_4K (0 << 14)
96*4882a593Smuzhiyun #define TCR_TG0_64K (1 << 14)
97*4882a593Smuzhiyun #define TCR_TG0_16K (2 << 14)
98*4882a593Smuzhiyun #define TCR_EPD1_DISABLE (1 << 23)
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #define TCR_EL1_RSVD (1 << 31)
101*4882a593Smuzhiyun #define TCR_EL2_RSVD (1 << 31 | 1 << 23)
102*4882a593Smuzhiyun #define TCR_EL3_RSVD (1 << 31 | 1 << 23)
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #ifndef __ASSEMBLY__
set_ttbr_tcr_mair(int el,u64 table,u64 tcr,u64 attr)105*4882a593Smuzhiyun static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun asm volatile("dsb sy");
108*4882a593Smuzhiyun if (el == 1) {
109*4882a593Smuzhiyun asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
110*4882a593Smuzhiyun asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
111*4882a593Smuzhiyun asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
112*4882a593Smuzhiyun } else if (el == 2) {
113*4882a593Smuzhiyun asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
114*4882a593Smuzhiyun asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
115*4882a593Smuzhiyun asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
116*4882a593Smuzhiyun } else if (el == 3) {
117*4882a593Smuzhiyun asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
118*4882a593Smuzhiyun asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
119*4882a593Smuzhiyun asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
120*4882a593Smuzhiyun } else {
121*4882a593Smuzhiyun hang();
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun asm volatile("isb");
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun struct mm_region {
127*4882a593Smuzhiyun u64 virt;
128*4882a593Smuzhiyun u64 phys;
129*4882a593Smuzhiyun u64 size;
130*4882a593Smuzhiyun u64 attrs;
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun extern struct mm_region *mem_map;
134*4882a593Smuzhiyun void setup_pgtables(void);
135*4882a593Smuzhiyun u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
136*4882a593Smuzhiyun #endif
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun #endif /* _ASM_ARMV8_MMU_H_ */
139