1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2017 3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun enum region_number { 9*4882a593Smuzhiyun REGION_0 = 0, 10*4882a593Smuzhiyun REGION_1, 11*4882a593Smuzhiyun REGION_2, 12*4882a593Smuzhiyun REGION_3, 13*4882a593Smuzhiyun REGION_4, 14*4882a593Smuzhiyun REGION_5, 15*4882a593Smuzhiyun REGION_6, 16*4882a593Smuzhiyun REGION_7, 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun enum ap { 20*4882a593Smuzhiyun NO_ACCESS = 0, 21*4882a593Smuzhiyun PRIV_RW_USR_NO, 22*4882a593Smuzhiyun PRIV_RW_USR_RO, 23*4882a593Smuzhiyun PRIV_RW_USR_RW, 24*4882a593Smuzhiyun UNPREDICTABLE, 25*4882a593Smuzhiyun PRIV_RO_USR_NO, 26*4882a593Smuzhiyun PRIV_RO_USR_RO, 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun enum mr_attr { 30*4882a593Smuzhiyun STRONG_ORDER = 0, 31*4882a593Smuzhiyun SHARED_WRITE_BUFFERED, 32*4882a593Smuzhiyun O_I_WT_NO_WR_ALLOC, 33*4882a593Smuzhiyun O_I_WB_NO_WR_ALLOC, 34*4882a593Smuzhiyun O_I_NON_CACHEABLE, 35*4882a593Smuzhiyun O_I_WB_RD_WR_ALLOC, 36*4882a593Smuzhiyun DEVICE_NON_SHARED, 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun enum size { 39*4882a593Smuzhiyun REGION_8MB = 22, 40*4882a593Smuzhiyun REGION_16MB, 41*4882a593Smuzhiyun REGION_32MB, 42*4882a593Smuzhiyun REGION_64MB, 43*4882a593Smuzhiyun REGION_128MB, 44*4882a593Smuzhiyun REGION_256MB, 45*4882a593Smuzhiyun REGION_512MB, 46*4882a593Smuzhiyun REGION_1GB, 47*4882a593Smuzhiyun REGION_2GB, 48*4882a593Smuzhiyun REGION_4GB, 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun enum xn { 52*4882a593Smuzhiyun XN_DIS = 0, 53*4882a593Smuzhiyun XN_EN, 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun struct mpu_region_config { 57*4882a593Smuzhiyun uint32_t start_addr; 58*4882a593Smuzhiyun enum region_number region_no; 59*4882a593Smuzhiyun enum xn xn; 60*4882a593Smuzhiyun enum ap ap; 61*4882a593Smuzhiyun enum mr_attr mr_attr; 62*4882a593Smuzhiyun enum size reg_size; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun void disable_mpu(void); 66*4882a593Smuzhiyun void enable_mpu(void); 67*4882a593Smuzhiyun void mpu_config(struct mpu_region_config *reg_config); 68