1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 - 2015 Xilinx, Inc. 3*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ASM_ARCH_SYS_PROTO_H 9*4882a593Smuzhiyun #define _ASM_ARCH_SYS_PROTO_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define PAYLOAD_ARG_CNT 5 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define ZYNQMP_CSU_SILICON_VER_MASK 0xF 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun enum { 16*4882a593Smuzhiyun IDCODE, 17*4882a593Smuzhiyun VERSION, 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun enum { 21*4882a593Smuzhiyun ZYNQMP_SILICON_V1, 22*4882a593Smuzhiyun ZYNQMP_SILICON_V2, 23*4882a593Smuzhiyun ZYNQMP_SILICON_V3, 24*4882a593Smuzhiyun ZYNQMP_SILICON_V4, 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun enum { 28*4882a593Smuzhiyun TCM_LOCK, 29*4882a593Smuzhiyun TCM_SPLIT, 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun int zynq_slcr_get_mio_pin_status(const char *periph); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun unsigned int zynqmp_get_silicon_version(void); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun void psu_init(void); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun void handoff_setup(void); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun void zynqmp_pmufw_version(void); 41*4882a593Smuzhiyun int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); 42*4882a593Smuzhiyun int zynqmp_mmio_read(const u32 address, u32 *value); 43*4882a593Smuzhiyun int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, 44*4882a593Smuzhiyun u32 *ret_payload); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun void initialize_tcm(bool mode); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun int chip_id(unsigned char id); 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif /* _ASM_ARCH_SYS_PROTO_H */ 51