1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 3*4882a593Smuzhiyun * Toradex, Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Authors: Stefan Agner 6*4882a593Smuzhiyun * Sanchayan Maity 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASM_ARCH_VF610_DDRMC_H 12*4882a593Smuzhiyun #define __ASM_ARCH_VF610_DDRMC_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct ddr3_jedec_timings { 15*4882a593Smuzhiyun u8 tinit; 16*4882a593Smuzhiyun u32 trst_pwron; 17*4882a593Smuzhiyun u32 cke_inactive; 18*4882a593Smuzhiyun u8 wrlat; 19*4882a593Smuzhiyun u8 caslat_lin; 20*4882a593Smuzhiyun u8 trc; 21*4882a593Smuzhiyun u8 trrd; 22*4882a593Smuzhiyun u8 tccd; 23*4882a593Smuzhiyun u8 tbst_int_interval; 24*4882a593Smuzhiyun u8 tfaw; 25*4882a593Smuzhiyun u8 trp; 26*4882a593Smuzhiyun u8 twtr; 27*4882a593Smuzhiyun u8 tras_min; 28*4882a593Smuzhiyun u8 tmrd; 29*4882a593Smuzhiyun u8 trtp; 30*4882a593Smuzhiyun u32 tras_max; 31*4882a593Smuzhiyun u8 tmod; 32*4882a593Smuzhiyun u8 tckesr; 33*4882a593Smuzhiyun u8 tcke; 34*4882a593Smuzhiyun u8 trcd_int; 35*4882a593Smuzhiyun u8 tras_lockout; 36*4882a593Smuzhiyun u8 tdal; 37*4882a593Smuzhiyun u8 bstlen; 38*4882a593Smuzhiyun u16 tdll; 39*4882a593Smuzhiyun u8 trp_ab; 40*4882a593Smuzhiyun u16 tref; 41*4882a593Smuzhiyun u8 trfc; 42*4882a593Smuzhiyun u16 tref_int; 43*4882a593Smuzhiyun u8 tpdex; 44*4882a593Smuzhiyun u8 txpdll; 45*4882a593Smuzhiyun u8 txsnr; 46*4882a593Smuzhiyun u16 txsr; 47*4882a593Smuzhiyun u8 cksrx; 48*4882a593Smuzhiyun u8 cksre; 49*4882a593Smuzhiyun u8 freq_chg_en; 50*4882a593Smuzhiyun u16 zqcl; 51*4882a593Smuzhiyun u16 zqinit; 52*4882a593Smuzhiyun u8 zqcs; 53*4882a593Smuzhiyun u8 ref_per_zq; 54*4882a593Smuzhiyun u8 zqcs_rotate; 55*4882a593Smuzhiyun u8 aprebit; 56*4882a593Smuzhiyun u8 cmd_age_cnt; 57*4882a593Smuzhiyun u8 age_cnt; 58*4882a593Smuzhiyun u8 q_fullness; 59*4882a593Smuzhiyun u8 odt_rd_mapcs0; 60*4882a593Smuzhiyun u8 odt_wr_mapcs0; 61*4882a593Smuzhiyun u8 wlmrd; 62*4882a593Smuzhiyun u8 wldqsen; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct ddrmc_cr_setting { 66*4882a593Smuzhiyun u32 setting; 67*4882a593Smuzhiyun int cr_rnum; /* CR register ; -1 for last entry */ 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct ddrmc_phy_setting { 71*4882a593Smuzhiyun u32 setting; 72*4882a593Smuzhiyun int phy_rnum; /* PHY register ; -1 for last entry */ 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count); 76*4882a593Smuzhiyun void ddrmc_phy_init(void); 77*4882a593Smuzhiyun void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, 78*4882a593Smuzhiyun struct ddrmc_cr_setting *board_cr_settings, 79*4882a593Smuzhiyun struct ddrmc_phy_setting *board_phy_settings, 80*4882a593Smuzhiyun int col_diff, int row_diff); 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif 83