1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* Tegra30 clock control functions */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _TEGRA30_CLOCK_H_ 10*4882a593Smuzhiyun #define _TEGRA30_CLOCK_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/arch-tegra/clock.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ 15*4882a593Smuzhiyun #define OSC_FREQ_SHIFT 28 16*4882a593Smuzhiyun #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun int tegra_plle_enable(void); 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #endif /* _TEGRA30_CLOCK_H_ */ 21