1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013-2015 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _TEGRA210_TEGRA_H_ 9*4882a593Smuzhiyun #define _TEGRA210_TEGRA_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */ 12*4882a593Smuzhiyun #define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ 13*4882a593Smuzhiyun #define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ 14*4882a593Smuzhiyun #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ 15*4882a593Smuzhiyun #define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ 16*4882a593Smuzhiyun #define NV_PA_SDRAM_BASE 0x80000000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <asm/arch-tegra/tegra.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #undef NVBOOTINFOTABLE_BCTSIZE 23*4882a593Smuzhiyun #undef NVBOOTINFOTABLE_BCTPTR 24*4882a593Smuzhiyun #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ 25*4882a593Smuzhiyun #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define MAX_NUM_CPU 4 28*4882a593Smuzhiyun #define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define TEGRA_USB1_BASE 0x7D000000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif /* _TEGRA210_TEGRA_H_ */ 33