1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013-2015 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _TEGRA210_SYSCTR_H_ 9*4882a593Smuzhiyun #define _TEGRA210_SYSCTR_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct sysctr_ctlr { 12*4882a593Smuzhiyun u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ 13*4882a593Smuzhiyun u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ 14*4882a593Smuzhiyun u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ 15*4882a593Smuzhiyun u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ 16*4882a593Smuzhiyun u32 reserved1[4]; /* 0x10 - 0x1C */ 17*4882a593Smuzhiyun u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ 18*4882a593Smuzhiyun u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ 19*4882a593Smuzhiyun u32 reserved2[1002]; /* 0x28 - 0xFCC */ 20*4882a593Smuzhiyun u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ 24*4882a593Smuzhiyun #define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif /* _TEGRA210_SYSCTR_H_ */ 27