xref: /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  *  (C) Copyright 2010,2011
3*4882a593Smuzhiyun  *  NVIDIA Corporation <www.nvidia.com>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef _TEGRA20_PINMUX_H_
9*4882a593Smuzhiyun #define _TEGRA20_PINMUX_H_
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun /*
12*4882a593Smuzhiyun  * Pin groups which we adjust. There are three basic attributes of each pin
13*4882a593Smuzhiyun  * group which use this enum:
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  *	- function
16*4882a593Smuzhiyun  *	- pullup / pulldown
17*4882a593Smuzhiyun  *	- tristate or normal
18*4882a593Smuzhiyun  */
19*4882a593Smuzhiyun enum pmux_pingrp {
20*4882a593Smuzhiyun 	/* APB_MISC_PP_TRISTATE_REG_A_0 */
21*4882a593Smuzhiyun 	PMUX_PINGRP_ATA,
22*4882a593Smuzhiyun 	PMUX_PINGRP_ATB,
23*4882a593Smuzhiyun 	PMUX_PINGRP_ATC,
24*4882a593Smuzhiyun 	PMUX_PINGRP_ATD,
25*4882a593Smuzhiyun 	PMUX_PINGRP_CDEV1,
26*4882a593Smuzhiyun 	PMUX_PINGRP_CDEV2,
27*4882a593Smuzhiyun 	PMUX_PINGRP_CSUS,
28*4882a593Smuzhiyun 	PMUX_PINGRP_DAP1,
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	PMUX_PINGRP_DAP2,
31*4882a593Smuzhiyun 	PMUX_PINGRP_DAP3,
32*4882a593Smuzhiyun 	PMUX_PINGRP_DAP4,
33*4882a593Smuzhiyun 	PMUX_PINGRP_DTA,
34*4882a593Smuzhiyun 	PMUX_PINGRP_DTB,
35*4882a593Smuzhiyun 	PMUX_PINGRP_DTC,
36*4882a593Smuzhiyun 	PMUX_PINGRP_DTD,
37*4882a593Smuzhiyun 	PMUX_PINGRP_DTE,
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	PMUX_PINGRP_GPU,
40*4882a593Smuzhiyun 	PMUX_PINGRP_GPV,
41*4882a593Smuzhiyun 	PMUX_PINGRP_I2CP,
42*4882a593Smuzhiyun 	PMUX_PINGRP_IRTX,
43*4882a593Smuzhiyun 	PMUX_PINGRP_IRRX,
44*4882a593Smuzhiyun 	PMUX_PINGRP_KBCB,
45*4882a593Smuzhiyun 	PMUX_PINGRP_KBCA,
46*4882a593Smuzhiyun 	PMUX_PINGRP_PMC,
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	PMUX_PINGRP_PTA,
49*4882a593Smuzhiyun 	PMUX_PINGRP_RM,
50*4882a593Smuzhiyun 	PMUX_PINGRP_KBCE,
51*4882a593Smuzhiyun 	PMUX_PINGRP_KBCF,
52*4882a593Smuzhiyun 	PMUX_PINGRP_GMA,
53*4882a593Smuzhiyun 	PMUX_PINGRP_GMC,
54*4882a593Smuzhiyun 	PMUX_PINGRP_SDIO1,
55*4882a593Smuzhiyun 	PMUX_PINGRP_OWC,
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
58*4882a593Smuzhiyun 	PMUX_PINGRP_GME,
59*4882a593Smuzhiyun 	PMUX_PINGRP_SDC,
60*4882a593Smuzhiyun 	PMUX_PINGRP_SDD,
61*4882a593Smuzhiyun 	PMUX_PINGRP_RESERVED0,
62*4882a593Smuzhiyun 	PMUX_PINGRP_SLXA,
63*4882a593Smuzhiyun 	PMUX_PINGRP_SLXC,
64*4882a593Smuzhiyun 	PMUX_PINGRP_SLXD,
65*4882a593Smuzhiyun 	PMUX_PINGRP_SLXK,
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	PMUX_PINGRP_SPDI,
68*4882a593Smuzhiyun 	PMUX_PINGRP_SPDO,
69*4882a593Smuzhiyun 	PMUX_PINGRP_SPIA,
70*4882a593Smuzhiyun 	PMUX_PINGRP_SPIB,
71*4882a593Smuzhiyun 	PMUX_PINGRP_SPIC,
72*4882a593Smuzhiyun 	PMUX_PINGRP_SPID,
73*4882a593Smuzhiyun 	PMUX_PINGRP_SPIE,
74*4882a593Smuzhiyun 	PMUX_PINGRP_SPIF,
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	PMUX_PINGRP_SPIG,
77*4882a593Smuzhiyun 	PMUX_PINGRP_SPIH,
78*4882a593Smuzhiyun 	PMUX_PINGRP_UAA,
79*4882a593Smuzhiyun 	PMUX_PINGRP_UAB,
80*4882a593Smuzhiyun 	PMUX_PINGRP_UAC,
81*4882a593Smuzhiyun 	PMUX_PINGRP_UAD,
82*4882a593Smuzhiyun 	PMUX_PINGRP_UCA,
83*4882a593Smuzhiyun 	PMUX_PINGRP_UCB,
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	PMUX_PINGRP_RESERVED1,
86*4882a593Smuzhiyun 	PMUX_PINGRP_ATE,
87*4882a593Smuzhiyun 	PMUX_PINGRP_KBCC,
88*4882a593Smuzhiyun 	PMUX_PINGRP_RESERVED2,
89*4882a593Smuzhiyun 	PMUX_PINGRP_RESERVED3,
90*4882a593Smuzhiyun 	PMUX_PINGRP_GMB,
91*4882a593Smuzhiyun 	PMUX_PINGRP_GMD,
92*4882a593Smuzhiyun 	PMUX_PINGRP_DDC,
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
95*4882a593Smuzhiyun 	PMUX_PINGRP_LD0,
96*4882a593Smuzhiyun 	PMUX_PINGRP_LD1,
97*4882a593Smuzhiyun 	PMUX_PINGRP_LD2,
98*4882a593Smuzhiyun 	PMUX_PINGRP_LD3,
99*4882a593Smuzhiyun 	PMUX_PINGRP_LD4,
100*4882a593Smuzhiyun 	PMUX_PINGRP_LD5,
101*4882a593Smuzhiyun 	PMUX_PINGRP_LD6,
102*4882a593Smuzhiyun 	PMUX_PINGRP_LD7,
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	PMUX_PINGRP_LD8,
105*4882a593Smuzhiyun 	PMUX_PINGRP_LD9,
106*4882a593Smuzhiyun 	PMUX_PINGRP_LD10,
107*4882a593Smuzhiyun 	PMUX_PINGRP_LD11,
108*4882a593Smuzhiyun 	PMUX_PINGRP_LD12,
109*4882a593Smuzhiyun 	PMUX_PINGRP_LD13,
110*4882a593Smuzhiyun 	PMUX_PINGRP_LD14,
111*4882a593Smuzhiyun 	PMUX_PINGRP_LD15,
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	PMUX_PINGRP_LD16,
114*4882a593Smuzhiyun 	PMUX_PINGRP_LD17,
115*4882a593Smuzhiyun 	PMUX_PINGRP_LHP0,
116*4882a593Smuzhiyun 	PMUX_PINGRP_LHP1,
117*4882a593Smuzhiyun 	PMUX_PINGRP_LHP2,
118*4882a593Smuzhiyun 	PMUX_PINGRP_LVP0,
119*4882a593Smuzhiyun 	PMUX_PINGRP_LVP1,
120*4882a593Smuzhiyun 	PMUX_PINGRP_HDINT,
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	PMUX_PINGRP_LM0,
123*4882a593Smuzhiyun 	PMUX_PINGRP_LM1,
124*4882a593Smuzhiyun 	PMUX_PINGRP_LVS,
125*4882a593Smuzhiyun 	PMUX_PINGRP_LSC0,
126*4882a593Smuzhiyun 	PMUX_PINGRP_LSC1,
127*4882a593Smuzhiyun 	PMUX_PINGRP_LSCK,
128*4882a593Smuzhiyun 	PMUX_PINGRP_LDC,
129*4882a593Smuzhiyun 	PMUX_PINGRP_LCSN,
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
132*4882a593Smuzhiyun 	PMUX_PINGRP_LSPI,
133*4882a593Smuzhiyun 	PMUX_PINGRP_LSDA,
134*4882a593Smuzhiyun 	PMUX_PINGRP_LSDI,
135*4882a593Smuzhiyun 	PMUX_PINGRP_LPW0,
136*4882a593Smuzhiyun 	PMUX_PINGRP_LPW1,
137*4882a593Smuzhiyun 	PMUX_PINGRP_LPW2,
138*4882a593Smuzhiyun 	PMUX_PINGRP_LDI,
139*4882a593Smuzhiyun 	PMUX_PINGRP_LHS,
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	PMUX_PINGRP_LPP,
142*4882a593Smuzhiyun 	PMUX_PINGRP_RESERVED4,
143*4882a593Smuzhiyun 	PMUX_PINGRP_KBCD,
144*4882a593Smuzhiyun 	PMUX_PINGRP_GPU7,
145*4882a593Smuzhiyun 	PMUX_PINGRP_DTF,
146*4882a593Smuzhiyun 	PMUX_PINGRP_UDA,
147*4882a593Smuzhiyun 	PMUX_PINGRP_CRTP,
148*4882a593Smuzhiyun 	PMUX_PINGRP_SDB,
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	/* these pin groups only have pullup and pull down control */
151*4882a593Smuzhiyun 	PMUX_PINGRP_CK32,
152*4882a593Smuzhiyun 	PMUX_PINGRP_DDRC,
153*4882a593Smuzhiyun 	PMUX_PINGRP_PMCA,
154*4882a593Smuzhiyun 	PMUX_PINGRP_PMCB,
155*4882a593Smuzhiyun 	PMUX_PINGRP_PMCC,
156*4882a593Smuzhiyun 	PMUX_PINGRP_PMCD,
157*4882a593Smuzhiyun 	PMUX_PINGRP_PMCE,
158*4882a593Smuzhiyun 	PMUX_PINGRP_XM2C,
159*4882a593Smuzhiyun 	PMUX_PINGRP_XM2D,
160*4882a593Smuzhiyun 	PMUX_PINGRP_COUNT,
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun /*
164*4882a593Smuzhiyun  * Functions which can be assigned to each of the pin groups. The values here
165*4882a593Smuzhiyun  * bear no relation to the values programmed into pinmux registers and are
166*4882a593Smuzhiyun  * purely a convenience. The translation is done through a table search.
167*4882a593Smuzhiyun  */
168*4882a593Smuzhiyun enum pmux_func {
169*4882a593Smuzhiyun 	PMUX_FUNC_DEFAULT,
170*4882a593Smuzhiyun 	PMUX_FUNC_AHB_CLK,
171*4882a593Smuzhiyun 	PMUX_FUNC_APB_CLK,
172*4882a593Smuzhiyun 	PMUX_FUNC_AUDIO_SYNC,
173*4882a593Smuzhiyun 	PMUX_FUNC_CRT,
174*4882a593Smuzhiyun 	PMUX_FUNC_DAP1,
175*4882a593Smuzhiyun 	PMUX_FUNC_DAP2,
176*4882a593Smuzhiyun 	PMUX_FUNC_DAP3,
177*4882a593Smuzhiyun 	PMUX_FUNC_DAP4,
178*4882a593Smuzhiyun 	PMUX_FUNC_DAP5,
179*4882a593Smuzhiyun 	PMUX_FUNC_DISPA,
180*4882a593Smuzhiyun 	PMUX_FUNC_DISPB,
181*4882a593Smuzhiyun 	PMUX_FUNC_EMC_TEST0_DLL,
182*4882a593Smuzhiyun 	PMUX_FUNC_EMC_TEST1_DLL,
183*4882a593Smuzhiyun 	PMUX_FUNC_GMI,
184*4882a593Smuzhiyun 	PMUX_FUNC_GMI_INT,
185*4882a593Smuzhiyun 	PMUX_FUNC_HDMI,
186*4882a593Smuzhiyun 	PMUX_FUNC_I2C,
187*4882a593Smuzhiyun 	PMUX_FUNC_I2C2,
188*4882a593Smuzhiyun 	PMUX_FUNC_I2C3,
189*4882a593Smuzhiyun 	PMUX_FUNC_IDE,
190*4882a593Smuzhiyun 	PMUX_FUNC_KBC,
191*4882a593Smuzhiyun 	PMUX_FUNC_MIO,
192*4882a593Smuzhiyun 	PMUX_FUNC_MIPI_HS,
193*4882a593Smuzhiyun 	PMUX_FUNC_NAND,
194*4882a593Smuzhiyun 	PMUX_FUNC_OSC,
195*4882a593Smuzhiyun 	PMUX_FUNC_OWR,
196*4882a593Smuzhiyun 	PMUX_FUNC_PCIE,
197*4882a593Smuzhiyun 	PMUX_FUNC_PLLA_OUT,
198*4882a593Smuzhiyun 	PMUX_FUNC_PLLC_OUT1,
199*4882a593Smuzhiyun 	PMUX_FUNC_PLLM_OUT1,
200*4882a593Smuzhiyun 	PMUX_FUNC_PLLP_OUT2,
201*4882a593Smuzhiyun 	PMUX_FUNC_PLLP_OUT3,
202*4882a593Smuzhiyun 	PMUX_FUNC_PLLP_OUT4,
203*4882a593Smuzhiyun 	PMUX_FUNC_PWM,
204*4882a593Smuzhiyun 	PMUX_FUNC_PWR_INTR,
205*4882a593Smuzhiyun 	PMUX_FUNC_PWR_ON,
206*4882a593Smuzhiyun 	PMUX_FUNC_RTCK,
207*4882a593Smuzhiyun 	PMUX_FUNC_SDIO1,
208*4882a593Smuzhiyun 	PMUX_FUNC_SDIO2,
209*4882a593Smuzhiyun 	PMUX_FUNC_SDIO3,
210*4882a593Smuzhiyun 	PMUX_FUNC_SDIO4,
211*4882a593Smuzhiyun 	PMUX_FUNC_SFLASH,
212*4882a593Smuzhiyun 	PMUX_FUNC_SPDIF,
213*4882a593Smuzhiyun 	PMUX_FUNC_SPI1,
214*4882a593Smuzhiyun 	PMUX_FUNC_SPI2,
215*4882a593Smuzhiyun 	PMUX_FUNC_SPI2_ALT,
216*4882a593Smuzhiyun 	PMUX_FUNC_SPI3,
217*4882a593Smuzhiyun 	PMUX_FUNC_SPI4,
218*4882a593Smuzhiyun 	PMUX_FUNC_TRACE,
219*4882a593Smuzhiyun 	PMUX_FUNC_TWC,
220*4882a593Smuzhiyun 	PMUX_FUNC_UARTA,
221*4882a593Smuzhiyun 	PMUX_FUNC_UARTB,
222*4882a593Smuzhiyun 	PMUX_FUNC_UARTC,
223*4882a593Smuzhiyun 	PMUX_FUNC_UARTD,
224*4882a593Smuzhiyun 	PMUX_FUNC_UARTE,
225*4882a593Smuzhiyun 	PMUX_FUNC_ULPI,
226*4882a593Smuzhiyun 	PMUX_FUNC_VI,
227*4882a593Smuzhiyun 	PMUX_FUNC_VI_SENSOR_CLK,
228*4882a593Smuzhiyun 	PMUX_FUNC_XIO,
229*4882a593Smuzhiyun 	PMUX_FUNC_RSVD1,
230*4882a593Smuzhiyun 	PMUX_FUNC_RSVD2,
231*4882a593Smuzhiyun 	PMUX_FUNC_RSVD3,
232*4882a593Smuzhiyun 	PMUX_FUNC_RSVD4,
233*4882a593Smuzhiyun 	PMUX_FUNC_COUNT,
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
237*4882a593Smuzhiyun #include <asm/arch-tegra/pinmux.h>
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun #endif /* _TEGRA20_PINMUX_H_ */
240