1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010,2011 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _TEGRA20_GP_PADCTRL_H_ 9*4882a593Smuzhiyun #define _TEGRA20_GP_PADCTRL_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/arch-tegra/gp_padctrl.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* APB_MISC_GP and padctrl registers */ 14*4882a593Smuzhiyun struct apb_misc_gp_ctlr { 15*4882a593Smuzhiyun u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ 16*4882a593Smuzhiyun u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ 17*4882a593Smuzhiyun u32 reserved0[22]; /* 0x08 - 0x5C: */ 18*4882a593Smuzhiyun u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ 19*4882a593Smuzhiyun u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ 20*4882a593Smuzhiyun u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ 21*4882a593Smuzhiyun u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ 22*4882a593Smuzhiyun u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ 23*4882a593Smuzhiyun u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ 24*4882a593Smuzhiyun u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */ 25*4882a593Smuzhiyun u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */ 26*4882a593Smuzhiyun u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */ 27*4882a593Smuzhiyun u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */ 28*4882a593Smuzhiyun u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */ 29*4882a593Smuzhiyun u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */ 30*4882a593Smuzhiyun u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */ 31*4882a593Smuzhiyun u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */ 32*4882a593Smuzhiyun u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */ 33*4882a593Smuzhiyun u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */ 34*4882a593Smuzhiyun u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */ 35*4882a593Smuzhiyun u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */ 36*4882a593Smuzhiyun u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */ 37*4882a593Smuzhiyun u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */ 38*4882a593Smuzhiyun u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */ 39*4882a593Smuzhiyun u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */ 40*4882a593Smuzhiyun u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */ 41*4882a593Smuzhiyun u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */ 42*4882a593Smuzhiyun u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */ 43*4882a593Smuzhiyun u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */ 44*4882a593Smuzhiyun u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */ 45*4882a593Smuzhiyun u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */ 46*4882a593Smuzhiyun u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */ 47*4882a593Smuzhiyun u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif /* _TEGRA20_GP_PADCTRL_H_ */ 51