1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2011 The Chromium OS Authors. 3*4882a593Smuzhiyun * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* Tegra20 clock PLL tables */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _CLOCK_TABLES_H_ 11*4882a593Smuzhiyun #define _CLOCK_TABLES_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* The PLLs supported by the hardware */ 14*4882a593Smuzhiyun enum clock_id { 15*4882a593Smuzhiyun CLOCK_ID_FIRST, 16*4882a593Smuzhiyun CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, 17*4882a593Smuzhiyun CLOCK_ID_MEMORY, 18*4882a593Smuzhiyun CLOCK_ID_PERIPH, 19*4882a593Smuzhiyun CLOCK_ID_AUDIO, 20*4882a593Smuzhiyun CLOCK_ID_USB, 21*4882a593Smuzhiyun CLOCK_ID_DISPLAY, 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* now the simple ones */ 24*4882a593Smuzhiyun CLOCK_ID_FIRST_SIMPLE, 25*4882a593Smuzhiyun CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, 26*4882a593Smuzhiyun CLOCK_ID_EPCI, 27*4882a593Smuzhiyun CLOCK_ID_SFROM32KHZ, 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* These are the base clocks (inputs to the Tegra SOC) */ 30*4882a593Smuzhiyun CLOCK_ID_32KHZ, 31*4882a593Smuzhiyun CLOCK_ID_OSC, 32*4882a593Smuzhiyun CLOCK_ID_CLK_M, 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun CLOCK_ID_COUNT, /* number of clocks */ 35*4882a593Smuzhiyun CLOCK_ID_NONE = -1, 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* The clocks supported by the hardware */ 39*4882a593Smuzhiyun enum periph_id { 40*4882a593Smuzhiyun PERIPH_ID_FIRST, 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Low word: 31:0 */ 43*4882a593Smuzhiyun PERIPH_ID_CPU = PERIPH_ID_FIRST, 44*4882a593Smuzhiyun PERIPH_ID_RESERVED1, 45*4882a593Smuzhiyun PERIPH_ID_RESERVED2, 46*4882a593Smuzhiyun PERIPH_ID_AC97, 47*4882a593Smuzhiyun PERIPH_ID_RTC, 48*4882a593Smuzhiyun PERIPH_ID_TMR, 49*4882a593Smuzhiyun PERIPH_ID_UART1, 50*4882a593Smuzhiyun PERIPH_ID_UART2, 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 8 */ 53*4882a593Smuzhiyun PERIPH_ID_GPIO, 54*4882a593Smuzhiyun PERIPH_ID_SDMMC2, 55*4882a593Smuzhiyun PERIPH_ID_SPDIF, 56*4882a593Smuzhiyun PERIPH_ID_I2S1, 57*4882a593Smuzhiyun PERIPH_ID_I2C1, 58*4882a593Smuzhiyun PERIPH_ID_NDFLASH, 59*4882a593Smuzhiyun PERIPH_ID_SDMMC1, 60*4882a593Smuzhiyun PERIPH_ID_SDMMC4, 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 16 */ 63*4882a593Smuzhiyun PERIPH_ID_TWC, 64*4882a593Smuzhiyun PERIPH_ID_PWM, 65*4882a593Smuzhiyun PERIPH_ID_I2S2, 66*4882a593Smuzhiyun PERIPH_ID_EPP, 67*4882a593Smuzhiyun PERIPH_ID_VI, 68*4882a593Smuzhiyun PERIPH_ID_2D, 69*4882a593Smuzhiyun PERIPH_ID_USBD, 70*4882a593Smuzhiyun PERIPH_ID_ISP, 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 24 */ 73*4882a593Smuzhiyun PERIPH_ID_3D, 74*4882a593Smuzhiyun PERIPH_ID_IDE, 75*4882a593Smuzhiyun PERIPH_ID_DISP2, 76*4882a593Smuzhiyun PERIPH_ID_DISP1, 77*4882a593Smuzhiyun PERIPH_ID_HOST1X, 78*4882a593Smuzhiyun PERIPH_ID_VCP, 79*4882a593Smuzhiyun PERIPH_ID_RESERVED30, 80*4882a593Smuzhiyun PERIPH_ID_CACHE2, 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Middle word: 63:32 */ 83*4882a593Smuzhiyun PERIPH_ID_MEM, 84*4882a593Smuzhiyun PERIPH_ID_AHBDMA, 85*4882a593Smuzhiyun PERIPH_ID_APBDMA, 86*4882a593Smuzhiyun PERIPH_ID_RESERVED35, 87*4882a593Smuzhiyun PERIPH_ID_KBC, 88*4882a593Smuzhiyun PERIPH_ID_STAT_MON, 89*4882a593Smuzhiyun PERIPH_ID_PMC, 90*4882a593Smuzhiyun PERIPH_ID_FUSE, 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* 40 */ 93*4882a593Smuzhiyun PERIPH_ID_KFUSE, 94*4882a593Smuzhiyun PERIPH_ID_SBC1, 95*4882a593Smuzhiyun PERIPH_ID_SNOR, 96*4882a593Smuzhiyun PERIPH_ID_SPI1, 97*4882a593Smuzhiyun PERIPH_ID_SBC2, 98*4882a593Smuzhiyun PERIPH_ID_XIO, 99*4882a593Smuzhiyun PERIPH_ID_SBC3, 100*4882a593Smuzhiyun PERIPH_ID_DVC_I2C, 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 48 */ 103*4882a593Smuzhiyun PERIPH_ID_DSI, 104*4882a593Smuzhiyun PERIPH_ID_TVO, 105*4882a593Smuzhiyun PERIPH_ID_MIPI, 106*4882a593Smuzhiyun PERIPH_ID_HDMI, 107*4882a593Smuzhiyun PERIPH_ID_CSI, 108*4882a593Smuzhiyun PERIPH_ID_TVDAC, 109*4882a593Smuzhiyun PERIPH_ID_I2C2, 110*4882a593Smuzhiyun PERIPH_ID_UART3, 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 56 */ 113*4882a593Smuzhiyun PERIPH_ID_RESERVED56, 114*4882a593Smuzhiyun PERIPH_ID_EMC, 115*4882a593Smuzhiyun PERIPH_ID_USB2, 116*4882a593Smuzhiyun PERIPH_ID_USB3, 117*4882a593Smuzhiyun PERIPH_ID_MPE, 118*4882a593Smuzhiyun PERIPH_ID_VDE, 119*4882a593Smuzhiyun PERIPH_ID_BSEA, 120*4882a593Smuzhiyun PERIPH_ID_BSEV, 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* Upper word 95:64 */ 123*4882a593Smuzhiyun PERIPH_ID_SPEEDO, 124*4882a593Smuzhiyun PERIPH_ID_UART4, 125*4882a593Smuzhiyun PERIPH_ID_UART5, 126*4882a593Smuzhiyun PERIPH_ID_I2C3, 127*4882a593Smuzhiyun PERIPH_ID_SBC4, 128*4882a593Smuzhiyun PERIPH_ID_SDMMC3, 129*4882a593Smuzhiyun PERIPH_ID_PCIE, 130*4882a593Smuzhiyun PERIPH_ID_OWR, 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* 72 */ 133*4882a593Smuzhiyun PERIPH_ID_AFI, 134*4882a593Smuzhiyun PERIPH_ID_CORESIGHT, 135*4882a593Smuzhiyun PERIPH_ID_PCIEXCLK, 136*4882a593Smuzhiyun PERIPH_ID_AVPUCQ, 137*4882a593Smuzhiyun PERIPH_ID_RESERVED76, 138*4882a593Smuzhiyun PERIPH_ID_RESERVED77, 139*4882a593Smuzhiyun PERIPH_ID_RESERVED78, 140*4882a593Smuzhiyun PERIPH_ID_RESERVED79, 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* 80 */ 143*4882a593Smuzhiyun PERIPH_ID_RESERVED80, 144*4882a593Smuzhiyun PERIPH_ID_RESERVED81, 145*4882a593Smuzhiyun PERIPH_ID_RESERVED82, 146*4882a593Smuzhiyun PERIPH_ID_RESERVED83, 147*4882a593Smuzhiyun PERIPH_ID_IRAMA, 148*4882a593Smuzhiyun PERIPH_ID_IRAMB, 149*4882a593Smuzhiyun PERIPH_ID_IRAMC, 150*4882a593Smuzhiyun PERIPH_ID_IRAMD, 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* 88 */ 153*4882a593Smuzhiyun PERIPH_ID_CRAM2, 154*4882a593Smuzhiyun PERIPH_ID_SYNC_CLK_DOUBLER, 155*4882a593Smuzhiyun PERIPH_ID_CLK_M_DOUBLER, 156*4882a593Smuzhiyun PERIPH_ID_RESERVED91, 157*4882a593Smuzhiyun PERIPH_ID_SUS_OUT, 158*4882a593Smuzhiyun PERIPH_ID_DEV2_OUT, 159*4882a593Smuzhiyun PERIPH_ID_DEV1_OUT, 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun PERIPH_ID_COUNT, 162*4882a593Smuzhiyun PERIPH_ID_NONE = -1, 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun enum pll_out_id { 166*4882a593Smuzhiyun PLL_OUT1, 167*4882a593Smuzhiyun PLL_OUT2, 168*4882a593Smuzhiyun PLL_OUT3, 169*4882a593Smuzhiyun PLL_OUT4 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ 173*4882a593Smuzhiyun #define PERIPH_REG(id) ((id) >> 5) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* Mask value for a clock (within PERIPH_REG(id)) */ 176*4882a593Smuzhiyun #define PERIPH_MASK(id) (1 << ((id) & 0x1f)) 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* return 1 if a PLL ID is in range, and not a simple PLL */ 179*4882a593Smuzhiyun #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ 180*4882a593Smuzhiyun (id) < CLOCK_ID_FIRST_SIMPLE) 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* return 1 if a peripheral ID is in range */ 183*4882a593Smuzhiyun #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ 184*4882a593Smuzhiyun (id) < PERIPH_ID_COUNT) 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #endif /* _CLOCK_TABLES_H_ */ 187