1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _TEGRA124_GPIO_H_ 9*4882a593Smuzhiyun #define _TEGRA124_GPIO_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports, 13*4882a593Smuzhiyun * each with 8 GPIOs. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ 16*4882a593Smuzhiyun #define TEGRA_GPIO_BANKS 8 /* number of banks */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <asm/arch-tegra/gpio.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* GPIO Controller registers for a single bank */ 21*4882a593Smuzhiyun struct gpio_ctlr_bank { 22*4882a593Smuzhiyun uint gpio_config[TEGRA_GPIO_PORTS]; 23*4882a593Smuzhiyun uint gpio_dir_out[TEGRA_GPIO_PORTS]; 24*4882a593Smuzhiyun uint gpio_out[TEGRA_GPIO_PORTS]; 25*4882a593Smuzhiyun uint gpio_in[TEGRA_GPIO_PORTS]; 26*4882a593Smuzhiyun uint gpio_int_status[TEGRA_GPIO_PORTS]; 27*4882a593Smuzhiyun uint gpio_int_enable[TEGRA_GPIO_PORTS]; 28*4882a593Smuzhiyun uint gpio_int_level[TEGRA_GPIO_PORTS]; 29*4882a593Smuzhiyun uint gpio_int_clear[TEGRA_GPIO_PORTS]; 30*4882a593Smuzhiyun uint gpio_masked_config[TEGRA_GPIO_PORTS]; 31*4882a593Smuzhiyun uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; 32*4882a593Smuzhiyun uint gpio_masked_out[TEGRA_GPIO_PORTS]; 33*4882a593Smuzhiyun uint gpio_masked_in[TEGRA_GPIO_PORTS]; 34*4882a593Smuzhiyun uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; 35*4882a593Smuzhiyun uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; 36*4882a593Smuzhiyun uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; 37*4882a593Smuzhiyun uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct gpio_ctlr { 41*4882a593Smuzhiyun struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif /* _TEGRA124_GPIO_H_ */ 45