1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010-2013 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _TEGRA124_FLOW_H_ 9*4882a593Smuzhiyun #define _TEGRA124_FLOW_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct flow_ctlr { 12*4882a593Smuzhiyun u32 halt_cpu_events; /* offset 0x00 */ 13*4882a593Smuzhiyun u32 halt_cop_events; /* offset 0x04 */ 14*4882a593Smuzhiyun u32 cpu_csr; /* offset 0x08 */ 15*4882a593Smuzhiyun u32 cop_csr; /* offset 0x0c */ 16*4882a593Smuzhiyun u32 xrq_events; /* offset 0x10 */ 17*4882a593Smuzhiyun u32 halt_cpu1_events; /* offset 0x14 */ 18*4882a593Smuzhiyun u32 cpu1_csr; /* offset 0x18 */ 19*4882a593Smuzhiyun u32 halt_cpu2_events; /* offset 0x1c */ 20*4882a593Smuzhiyun u32 cpu2_csr; /* offset 0x20 */ 21*4882a593Smuzhiyun u32 halt_cpu3_events; /* offset 0x24 */ 22*4882a593Smuzhiyun u32 cpu3_csr; /* offset 0x28 */ 23*4882a593Smuzhiyun u32 cluster_control; /* offset 0x2c */ 24*4882a593Smuzhiyun u32 halt_cop1_events; /* offset 0x30 */ 25*4882a593Smuzhiyun u32 halt_cop1_csr; /* offset 0x34 */ 26*4882a593Smuzhiyun u32 cpu_pwr_csr; /* offset 0x38 */ 27*4882a593Smuzhiyun u32 mpid; /* offset 0x3c */ 28*4882a593Smuzhiyun u32 ram_repair; /* offset 0x40 */ 29*4882a593Smuzhiyun u32 flow_dbg_sel; /* offset 0x44 */ 30*4882a593Smuzhiyun u32 flow_dbg_cnt0; /* offset 0x48 */ 31*4882a593Smuzhiyun u32 flow_dbg_cnt1; /* offset 0x4c */ 32*4882a593Smuzhiyun u32 flow_dbg_qual; /* offset 0x50 */ 33*4882a593Smuzhiyun u32 flow_ctlr_spare; /* offset 0x54 */ 34*4882a593Smuzhiyun u32 ram_repair_cluster1;/* offset 0x58 */ 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* HALT_COP_EVENTS_0, 0x04 */ 38*4882a593Smuzhiyun #define EVENT_MSEC (1 << 24) 39*4882a593Smuzhiyun #define EVENT_USEC (1 << 25) 40*4882a593Smuzhiyun #define EVENT_JTAG (1 << 28) 41*4882a593Smuzhiyun #define EVENT_MODE_STOP (2 << 29) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ 44*4882a593Smuzhiyun #define ACTIVE_LP (1 << 0) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* CPUn_CSR_0 */ 47*4882a593Smuzhiyun #define CSR_ENABLE (1 << 0) 48*4882a593Smuzhiyun #define CSR_IMMEDIATE_WAKE (1 << 3) 49*4882a593Smuzhiyun #define CSR_WAIT_WFI_SHIFT 8 50*4882a593Smuzhiyun #define CSR_PWR_OFF_STS (1 << 16) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* RAM_REPAIR, 0x40, 0x58 */ 53*4882a593Smuzhiyun enum { 54*4882a593Smuzhiyun RAM_REPAIR_REQ = 0x1 << 0, 55*4882a593Smuzhiyun RAM_REPAIR_STS = 0x1 << 1, 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif /* _TEGRA124_FLOW_H_ */ 59