1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _TEGRA114_H_ 8*4882a593Smuzhiyun #define _TEGRA114_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ 11*4882a593Smuzhiyun #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ 12*4882a593Smuzhiyun #define NV_PA_MC_BASE 0x70019000 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <asm/arch-tegra/tegra.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #undef NVBOOTINFOTABLE_BCTSIZE 19*4882a593Smuzhiyun #undef NVBOOTINFOTABLE_BCTPTR 20*4882a593Smuzhiyun #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ 21*4882a593Smuzhiyun #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MAX_NUM_CPU 4 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif /* TEGRA114_H */ 26