1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _TEGRA114_GPIO_H_ 8*4882a593Smuzhiyun #define _TEGRA114_GPIO_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports, 12*4882a593Smuzhiyun * each with 8 GPIOs. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ 15*4882a593Smuzhiyun #define TEGRA_GPIO_BANKS 8 /* number of banks */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <asm/arch-tegra/gpio.h> 18*4882a593Smuzhiyun #include <asm/arch-tegra30/gpio.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #endif /* _TEGRA114_GPIO_H_ */ 21