1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _TEGRA114_FLOW_H_ 8*4882a593Smuzhiyun #define _TEGRA114_FLOW_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct flow_ctlr { 11*4882a593Smuzhiyun u32 halt_cpu_events; 12*4882a593Smuzhiyun u32 halt_cop_events; 13*4882a593Smuzhiyun u32 cpu_csr; 14*4882a593Smuzhiyun u32 cop_csr; 15*4882a593Smuzhiyun u32 xrq_events; 16*4882a593Smuzhiyun u32 halt_cpu1_events; 17*4882a593Smuzhiyun u32 cpu1_csr; 18*4882a593Smuzhiyun u32 halt_cpu2_events; 19*4882a593Smuzhiyun u32 cpu2_csr; 20*4882a593Smuzhiyun u32 halt_cpu3_events; 21*4882a593Smuzhiyun u32 cpu3_csr; 22*4882a593Smuzhiyun u32 cluster_control; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif /* _TEGRA114_FLOW_H_ */ 26