1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010,2011 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _UART_H_ 9*4882a593Smuzhiyun #define _UART_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* UART registers */ 12*4882a593Smuzhiyun struct uart_ctlr { 13*4882a593Smuzhiyun uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */ 14*4882a593Smuzhiyun uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */ 15*4882a593Smuzhiyun uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */ 16*4882a593Smuzhiyun uint uart_lcr; /* UART_LCR_0, offset 0C */ 17*4882a593Smuzhiyun uint uart_mcr; /* UART_MCR_0, offset 10 */ 18*4882a593Smuzhiyun uint uart_lsr; /* UART_LSR_0, offset 14 */ 19*4882a593Smuzhiyun uint uart_msr; /* UART_MSR_0, offset 18 */ 20*4882a593Smuzhiyun uint uart_spr; /* UART_SPR_0, offset 1C */ 21*4882a593Smuzhiyun uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */ 22*4882a593Smuzhiyun uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/ 23*4882a593Smuzhiyun uint uart_asr; /* UART_ASR_0, offset 3C */ 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define NVRM_PLLP_FIXED_FREQ_KHZ 216000 27*4882a593Smuzhiyun #define NV_DEFAULT_DEBUG_BAUD 115200 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif /* UART_H */ 32