1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 SAMSUNG Electronics 3*4882a593Smuzhiyun * Minkyu Kang <mk7.kang@samsung.com> 4*4882a593Smuzhiyun * Portions Copyright (C) 2011-2012 NVIDIA Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __TEGRA_MMC_H_ 10*4882a593Smuzhiyun #define __TEGRA_MMC_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <common.h> 13*4882a593Smuzhiyun #include <clk.h> 14*4882a593Smuzhiyun #include <reset.h> 15*4882a593Smuzhiyun #include <fdtdec.h> 16*4882a593Smuzhiyun #include <asm/gpio.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* for mmc_config definition */ 19*4882a593Smuzhiyun #include <mmc.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 22*4882a593Smuzhiyun struct tegra_mmc { 23*4882a593Smuzhiyun unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ 24*4882a593Smuzhiyun unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ 25*4882a593Smuzhiyun unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ 26*4882a593Smuzhiyun unsigned int argument; /* _ARGUMENT_0 */ 27*4882a593Smuzhiyun unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ 28*4882a593Smuzhiyun unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ 29*4882a593Smuzhiyun unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ 30*4882a593Smuzhiyun unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ 31*4882a593Smuzhiyun unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ 32*4882a593Smuzhiyun unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ 33*4882a593Smuzhiyun unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ 34*4882a593Smuzhiyun unsigned int prnsts; /* _PRESENT_STATE_0 */ 35*4882a593Smuzhiyun unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ 36*4882a593Smuzhiyun unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ 37*4882a593Smuzhiyun unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ 38*4882a593Smuzhiyun unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ 39*4882a593Smuzhiyun unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ 40*4882a593Smuzhiyun unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ 41*4882a593Smuzhiyun unsigned char swrst; /* _SW_RESET_ 31:24 */ 42*4882a593Smuzhiyun unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ 43*4882a593Smuzhiyun unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ 44*4882a593Smuzhiyun unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ 45*4882a593Smuzhiyun unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ 46*4882a593Smuzhiyun unsigned char res1[2]; /* _RESERVED 31:16 */ 47*4882a593Smuzhiyun unsigned int capareg; /* _CAPABILITIES_0 */ 48*4882a593Smuzhiyun unsigned char res2[4]; /* RESERVED, offset 44h-47h */ 49*4882a593Smuzhiyun unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ 50*4882a593Smuzhiyun unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ 51*4882a593Smuzhiyun unsigned short setacmd12err; /* offset 50h */ 52*4882a593Smuzhiyun unsigned short setinterr; /* offset 52h */ 53*4882a593Smuzhiyun unsigned char admaerr; /* offset 54h */ 54*4882a593Smuzhiyun unsigned char res4[3]; /* RESERVED, offset 55h-57h */ 55*4882a593Smuzhiyun unsigned long admaaddr; /* offset 58h-5Fh */ 56*4882a593Smuzhiyun unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */ 57*4882a593Smuzhiyun unsigned short slotintstatus; /* offset FCh */ 58*4882a593Smuzhiyun unsigned short hcver; /* HOST Version */ 59*4882a593Smuzhiyun unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */ 60*4882a593Smuzhiyun unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */ 61*4882a593Smuzhiyun unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */ 62*4882a593Smuzhiyun unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */ 63*4882a593Smuzhiyun unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */ 64*4882a593Smuzhiyun unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */ 65*4882a593Smuzhiyun unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */ 66*4882a593Smuzhiyun unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */ 67*4882a593Smuzhiyun unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */ 68*4882a593Smuzhiyun unsigned int res6[47]; /* 0x124 ~ 0x1DC */ 69*4882a593Smuzhiyun unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */ 70*4882a593Smuzhiyun unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */ 71*4882a593Smuzhiyun unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */ 72*4882a593Smuzhiyun unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */ 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0) 76*4882a593Smuzhiyun #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1) 77*4882a593Smuzhiyun #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1) 78*4882a593Smuzhiyun #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) 81*4882a593Smuzhiyun #define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) 82*4882a593Smuzhiyun #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) 83*4882a593Smuzhiyun #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) 86*4882a593Smuzhiyun #define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) 87*4882a593Smuzhiyun #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) 88*4882a593Smuzhiyun #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) 89*4882a593Smuzhiyun #define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) 92*4882a593Smuzhiyun #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) 93*4882a593Smuzhiyun #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) 94*4882a593Smuzhiyun #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) 95*4882a593Smuzhiyun #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) 98*4882a593Smuzhiyun #define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) 99*4882a593Smuzhiyun #define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) 102*4882a593Smuzhiyun #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) 105*4882a593Smuzhiyun #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) 106*4882a593Smuzhiyun #define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 109*4882a593Smuzhiyun #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK (1 << 17) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) 114*4882a593Smuzhiyun #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) 115*4882a593Smuzhiyun #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) 118*4882a593Smuzhiyun #define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) 119*4882a593Smuzhiyun #define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) 120*4882a593Smuzhiyun #define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) 121*4882a593Smuzhiyun #define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) 124*4882a593Smuzhiyun #define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) 125*4882a593Smuzhiyun #define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) 126*4882a593Smuzhiyun #define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) 127*4882a593Smuzhiyun #define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* SDMMC1/3 settings from section 24.6 of T30 TRM */ 132*4882a593Smuzhiyun #define MEMCOMP_PADCTRL_VREF 7 133*4882a593Smuzhiyun #define AUTO_CAL_ENABLED (1 << 29) 134*4882a593Smuzhiyun #define AUTO_CAL_PD_OFFSET (0x70 << 8) 135*4882a593Smuzhiyun #define AUTO_CAL_PU_OFFSET (0x62 << 0) 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 138*4882a593Smuzhiyun #endif /* __TEGRA_MMC_H_ */ 139