1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010-2015 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _TEGRA_H_ 9*4882a593Smuzhiyun #define _TEGRA_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define NV_PA_ARM_PERIPHBASE 0x50040000 12*4882a593Smuzhiyun #define NV_PA_PG_UP_BASE 0x60000000 13*4882a593Smuzhiyun #define NV_PA_TMRUS_BASE 0x60005010 14*4882a593Smuzhiyun #define NV_PA_CLK_RST_BASE 0x60006000 15*4882a593Smuzhiyun #define NV_PA_FLOW_BASE 0x60007000 16*4882a593Smuzhiyun #define NV_PA_GPIO_BASE 0x6000D000 17*4882a593Smuzhiyun #define NV_PA_EVP_BASE 0x6000F000 18*4882a593Smuzhiyun #define NV_PA_APB_MISC_BASE 0x70000000 19*4882a593Smuzhiyun #define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) 20*4882a593Smuzhiyun #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) 21*4882a593Smuzhiyun #define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) 22*4882a593Smuzhiyun #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) 23*4882a593Smuzhiyun #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) 24*4882a593Smuzhiyun #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) 25*4882a593Smuzhiyun #define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000) 26*4882a593Smuzhiyun #define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) 27*4882a593Smuzhiyun #define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400) 28*4882a593Smuzhiyun #define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600) 29*4882a593Smuzhiyun #define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800) 30*4882a593Smuzhiyun #define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00) 31*4882a593Smuzhiyun #define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) 32*4882a593Smuzhiyun #define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) 33*4882a593Smuzhiyun #define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) 34*4882a593Smuzhiyun #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) 35*4882a593Smuzhiyun #define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) 36*4882a593Smuzhiyun #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) 37*4882a593Smuzhiyun #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ 38*4882a593Smuzhiyun defined(CONFIG_TEGRA114) 39*4882a593Smuzhiyun #define NV_PA_CSITE_BASE 0x70040000 40*4882a593Smuzhiyun #else 41*4882a593Smuzhiyun #define NV_PA_CSITE_BASE 0x70800000 42*4882a593Smuzhiyun #endif 43*4882a593Smuzhiyun #define TEGRA_USB_ADDR_MASK 0xFFFFC000 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE 46*4882a593Smuzhiyun #define LOW_LEVEL_SRAM_STACK 0x4000FFFC 47*4882a593Smuzhiyun #define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) 48*4882a593Smuzhiyun #define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096) 49*4882a593Smuzhiyun #define PG_UP_TAG_AVP 0xAAAAAAAA 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 52*4882a593Smuzhiyun struct timerus { 53*4882a593Smuzhiyun unsigned int cntr_1us; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ 57*4882a593Smuzhiyun #define NV_WB_RUN_ADDRESS 0x40020000 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define NVBOOTTYPE_RECOVERY 2 /* BR entered RCM */ 60*4882a593Smuzhiyun #define NVBOOTINFOTABLE_BOOTTYPE 0xC /* Boot type in BIT in IRAM */ 61*4882a593Smuzhiyun #define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ 62*4882a593Smuzhiyun #define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* These are the available SKUs (product types) for Tegra */ 65*4882a593Smuzhiyun enum { 66*4882a593Smuzhiyun SKU_ID_T20_7 = 0x7, 67*4882a593Smuzhiyun SKU_ID_T20 = 0x8, 68*4882a593Smuzhiyun SKU_ID_T25SE = 0x14, 69*4882a593Smuzhiyun SKU_ID_AP25 = 0x17, 70*4882a593Smuzhiyun SKU_ID_T25 = 0x18, 71*4882a593Smuzhiyun SKU_ID_AP25E = 0x1b, 72*4882a593Smuzhiyun SKU_ID_T25E = 0x1c, 73*4882a593Smuzhiyun SKU_ID_T33 = 0x80, 74*4882a593Smuzhiyun SKU_ID_T30 = 0x81, /* Cardhu value */ 75*4882a593Smuzhiyun SKU_ID_TM30MQS_P_A3 = 0xb1, 76*4882a593Smuzhiyun SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ 77*4882a593Smuzhiyun SKU_ID_T114_1 = 0x01, 78*4882a593Smuzhiyun SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */ 79*4882a593Smuzhiyun SKU_ID_T210_ENG = 0x00, /* unfused value TBD */ 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* 83*4882a593Smuzhiyun * These are used to distinguish SOC types for setting up clocks. Mostly 84*4882a593Smuzhiyun * we can tell the clocking required by looking at the SOC sku_id, but 85*4882a593Smuzhiyun * for T30 it is a user option as to whether to run PLLP in fast or slow 86*4882a593Smuzhiyun * mode, so we have two options there. 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun enum { 89*4882a593Smuzhiyun TEGRA_SOC_T20, 90*4882a593Smuzhiyun TEGRA_SOC_T25, 91*4882a593Smuzhiyun TEGRA_SOC_T30, 92*4882a593Smuzhiyun TEGRA_SOC_T114, 93*4882a593Smuzhiyun TEGRA_SOC_T124, 94*4882a593Smuzhiyun TEGRA_SOC_T210, 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun TEGRA_SOC_CNT, 97*4882a593Smuzhiyun TEGRA_SOC_UNKNOWN = -1, 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* Tegra system controller (SYSCON) devices */ 101*4882a593Smuzhiyun enum { 102*4882a593Smuzhiyun TEGRA_SYSCON_PMC, 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #else /* __ASSEMBLY__ */ 106*4882a593Smuzhiyun #define PRM_RSTCTRL NV_PA_PMC_BASE 107*4882a593Smuzhiyun #endif 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #endif /* TEGRA_H */ 110