1*4882a593Smuzhiyun #ifndef _TEGRA_POWERGATE_H_ 2*4882a593Smuzhiyun #define _TEGRA_POWERGATE_H_ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #include <asm/arch/clock.h> 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun enum tegra_powergate { 7*4882a593Smuzhiyun TEGRA_POWERGATE_CPU, 8*4882a593Smuzhiyun TEGRA_POWERGATE_3D, 9*4882a593Smuzhiyun TEGRA_POWERGATE_VENC, 10*4882a593Smuzhiyun TEGRA_POWERGATE_PCIE, 11*4882a593Smuzhiyun TEGRA_POWERGATE_VDEC, 12*4882a593Smuzhiyun TEGRA_POWERGATE_L2, 13*4882a593Smuzhiyun TEGRA_POWERGATE_MPE, 14*4882a593Smuzhiyun TEGRA_POWERGATE_HEG, 15*4882a593Smuzhiyun TEGRA_POWERGATE_SATA, 16*4882a593Smuzhiyun TEGRA_POWERGATE_CPU1, 17*4882a593Smuzhiyun TEGRA_POWERGATE_CPU2, 18*4882a593Smuzhiyun TEGRA_POWERGATE_CPU3, 19*4882a593Smuzhiyun TEGRA_POWERGATE_CELP, 20*4882a593Smuzhiyun TEGRA_POWERGATE_3D1, 21*4882a593Smuzhiyun TEGRA_POWERGATE_CPU0, 22*4882a593Smuzhiyun TEGRA_POWERGATE_C0NC, 23*4882a593Smuzhiyun TEGRA_POWERGATE_C1NC, 24*4882a593Smuzhiyun TEGRA_POWERGATE_SOR, 25*4882a593Smuzhiyun TEGRA_POWERGATE_DIS, 26*4882a593Smuzhiyun TEGRA_POWERGATE_DISB, 27*4882a593Smuzhiyun TEGRA_POWERGATE_XUSBA, 28*4882a593Smuzhiyun TEGRA_POWERGATE_XUSBB, 29*4882a593Smuzhiyun TEGRA_POWERGATE_XUSBC, 30*4882a593Smuzhiyun TEGRA_POWERGATE_VIC, 31*4882a593Smuzhiyun TEGRA_POWERGATE_IRAM, 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun int tegra_powergate_sequence_power_up(enum tegra_powergate id, 35*4882a593Smuzhiyun enum periph_id periph); 36*4882a593Smuzhiyun int tegra_powergate_power_on(enum tegra_powergate id); 37*4882a593Smuzhiyun int tegra_powergate_power_off(enum tegra_powergate id); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif 40