1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2012 The Chromium OS Authors. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _GP_PADCTRL_H_ 8*4882a593Smuzhiyun #define _GP_PADCTRL_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* APB_MISC_PP registers */ 11*4882a593Smuzhiyun struct apb_misc_pp_ctlr { 12*4882a593Smuzhiyun u32 reserved0[2]; 13*4882a593Smuzhiyun u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ 14*4882a593Smuzhiyun u32 reserved1[6]; /* 0x0c .. 0x20 */ 15*4882a593Smuzhiyun u32 cfg_ctl; /* 0x24 */ 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ 19*4882a593Smuzhiyun #define RAM_CODE_SHIFT 4 20*4882a593Smuzhiyun #define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif 23