1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 Chen-Yu Tsai <wens@csie.org> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _SUNXI_TZPC_H 8*4882a593Smuzhiyun #define _SUNXI_TZPC_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 11*4882a593Smuzhiyun struct sunxi_tzpc { 12*4882a593Smuzhiyun u32 r0size; /* 0x00 Size of secure RAM region */ 13*4882a593Smuzhiyun u32 decport0_status; /* 0x04 Status of decode protection port 0 */ 14*4882a593Smuzhiyun u32 decport0_set; /* 0x08 Set decode protection port 0 */ 15*4882a593Smuzhiyun u32 decport0_clear; /* 0x0c Clear decode protection port 0 */ 16*4882a593Smuzhiyun /* For A80 and later SoCs */ 17*4882a593Smuzhiyun u32 decport1_status; /* 0x10 Status of decode protection port 1 */ 18*4882a593Smuzhiyun u32 decport1_set; /* 0x14 Set decode protection port 1 */ 19*4882a593Smuzhiyun u32 decport1_clear; /* 0x18 Clear decode protection port 1 */ 20*4882a593Smuzhiyun u32 decport2_status; /* 0x1c Status of decode protection port 2 */ 21*4882a593Smuzhiyun u32 decport2_set; /* 0x20 Set decode protection port 2 */ 22*4882a593Smuzhiyun u32 decport2_clear; /* 0x24 Clear decode protection port 2 */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun #endif 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define SUN6I_TZPC_DECPORT0_RTC (1 << 1) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define SUN8I_H3_TZPC_DECPORT0_ALL 0xbe 29*4882a593Smuzhiyun #define SUN8I_H3_TZPC_DECPORT1_ALL 0xff 30*4882a593Smuzhiyun #define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun void tzpc_init(void); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* _SUNXI_TZPC_H */ 35