1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2007-2011 3*4882a593Smuzhiyun * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4*4882a593Smuzhiyun * Tom Cubie <tangliang@allwinnertech.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Configuration settings for the Allwinner A10-evb board. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _SUNXI_TIMER_H_ 12*4882a593Smuzhiyun #define _SUNXI_TIMER_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <linux/types.h> 17*4882a593Smuzhiyun #include <asm/arch/watchdog.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* General purpose timer */ 20*4882a593Smuzhiyun struct sunxi_timer { 21*4882a593Smuzhiyun u32 ctl; 22*4882a593Smuzhiyun u32 inter; 23*4882a593Smuzhiyun u32 val; 24*4882a593Smuzhiyun u8 res[4]; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Audio video sync*/ 28*4882a593Smuzhiyun struct sunxi_avs { 29*4882a593Smuzhiyun u32 ctl; /* 0x80 */ 30*4882a593Smuzhiyun u32 cnt0; /* 0x84 */ 31*4882a593Smuzhiyun u32 cnt1; /* 0x88 */ 32*4882a593Smuzhiyun u32 div; /* 0x8c */ 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 64 bit counter */ 36*4882a593Smuzhiyun struct sunxi_64cnt { 37*4882a593Smuzhiyun u32 ctl; /* 0xa0 */ 38*4882a593Smuzhiyun u32 lo; /* 0xa4 */ 39*4882a593Smuzhiyun u32 hi; /* 0xa8 */ 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Rtc */ 43*4882a593Smuzhiyun struct sunxi_rtc { 44*4882a593Smuzhiyun u32 ctl; /* 0x100 */ 45*4882a593Smuzhiyun u32 yymmdd; /* 0x104 */ 46*4882a593Smuzhiyun u32 hhmmss; /* 0x108 */ 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Alarm */ 50*4882a593Smuzhiyun struct sunxi_alarm { 51*4882a593Smuzhiyun u32 ddhhmmss; /* 0x10c */ 52*4882a593Smuzhiyun u32 hhmmss; /* 0x110 */ 53*4882a593Smuzhiyun u32 en; /* 0x114 */ 54*4882a593Smuzhiyun u32 irqen; /* 0x118 */ 55*4882a593Smuzhiyun u32 irqsta; /* 0x11c */ 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Timer general purpose register */ 59*4882a593Smuzhiyun struct sunxi_tgp { 60*4882a593Smuzhiyun u32 tgpd; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct sunxi_timer_reg { 64*4882a593Smuzhiyun u32 tirqen; /* 0x00 */ 65*4882a593Smuzhiyun u32 tirqsta; /* 0x04 */ 66*4882a593Smuzhiyun u8 res1[8]; 67*4882a593Smuzhiyun struct sunxi_timer timer[6]; /* We have 6 timers */ 68*4882a593Smuzhiyun u8 res2[16]; 69*4882a593Smuzhiyun struct sunxi_avs avs; 70*4882a593Smuzhiyun #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) 71*4882a593Smuzhiyun struct sunxi_wdog wdog; /* 0x90 */ 72*4882a593Smuzhiyun /* XXX the following is not accurate for sun5i/sun7i */ 73*4882a593Smuzhiyun struct sunxi_64cnt cnt64; /* 0xa0 */ 74*4882a593Smuzhiyun u8 res4[0x58]; 75*4882a593Smuzhiyun struct sunxi_rtc rtc; 76*4882a593Smuzhiyun struct sunxi_alarm alarm; 77*4882a593Smuzhiyun struct sunxi_tgp tgp[4]; 78*4882a593Smuzhiyun u8 res5[8]; 79*4882a593Smuzhiyun u32 cpu_cfg; 80*4882a593Smuzhiyun #elif defined(CONFIG_SUNXI_GEN_SUN6I) 81*4882a593Smuzhiyun u8 res3[16]; 82*4882a593Smuzhiyun struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ 83*4882a593Smuzhiyun #endif 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif 89