1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Sunxi platform timing controller register and constant defines 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> 5*4882a593Smuzhiyun * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _LCDC_H 11*4882a593Smuzhiyun #define _LCDC_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <fdtdec.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct sunxi_lcdc_reg { 16*4882a593Smuzhiyun u32 ctrl; /* 0x00 */ 17*4882a593Smuzhiyun u32 int0; /* 0x04 */ 18*4882a593Smuzhiyun u32 int1; /* 0x08 */ 19*4882a593Smuzhiyun u8 res0[0x04]; /* 0x0c */ 20*4882a593Smuzhiyun u32 tcon0_frm_ctrl; /* 0x10 */ 21*4882a593Smuzhiyun u32 tcon0_frm_seed[6]; /* 0x14 */ 22*4882a593Smuzhiyun u32 tcon0_frm_table[4]; /* 0x2c */ 23*4882a593Smuzhiyun u8 res1[4]; /* 0x3c */ 24*4882a593Smuzhiyun u32 tcon0_ctrl; /* 0x40 */ 25*4882a593Smuzhiyun u32 tcon0_dclk; /* 0x44 */ 26*4882a593Smuzhiyun u32 tcon0_timing_active; /* 0x48 */ 27*4882a593Smuzhiyun u32 tcon0_timing_h; /* 0x4c */ 28*4882a593Smuzhiyun u32 tcon0_timing_v; /* 0x50 */ 29*4882a593Smuzhiyun u32 tcon0_timing_sync; /* 0x54 */ 30*4882a593Smuzhiyun u32 tcon0_hv_intf; /* 0x58 */ 31*4882a593Smuzhiyun u8 res2[0x04]; /* 0x5c */ 32*4882a593Smuzhiyun u32 tcon0_cpu_intf; /* 0x60 */ 33*4882a593Smuzhiyun u32 tcon0_cpu_wr_dat; /* 0x64 */ 34*4882a593Smuzhiyun u32 tcon0_cpu_rd_dat0; /* 0x68 */ 35*4882a593Smuzhiyun u32 tcon0_cpu_rd_dat1; /* 0x6c */ 36*4882a593Smuzhiyun u32 tcon0_ttl_timing0; /* 0x70 */ 37*4882a593Smuzhiyun u32 tcon0_ttl_timing1; /* 0x74 */ 38*4882a593Smuzhiyun u32 tcon0_ttl_timing2; /* 0x78 */ 39*4882a593Smuzhiyun u32 tcon0_ttl_timing3; /* 0x7c */ 40*4882a593Smuzhiyun u32 tcon0_ttl_timing4; /* 0x80 */ 41*4882a593Smuzhiyun u32 tcon0_lvds_intf; /* 0x84 */ 42*4882a593Smuzhiyun u32 tcon0_io_polarity; /* 0x88 */ 43*4882a593Smuzhiyun u32 tcon0_io_tristate; /* 0x8c */ 44*4882a593Smuzhiyun u32 tcon1_ctrl; /* 0x90 */ 45*4882a593Smuzhiyun u32 tcon1_timing_source; /* 0x94 */ 46*4882a593Smuzhiyun u32 tcon1_timing_scale; /* 0x98 */ 47*4882a593Smuzhiyun u32 tcon1_timing_out; /* 0x9c */ 48*4882a593Smuzhiyun u32 tcon1_timing_h; /* 0xa0 */ 49*4882a593Smuzhiyun u32 tcon1_timing_v; /* 0xa4 */ 50*4882a593Smuzhiyun u32 tcon1_timing_sync; /* 0xa8 */ 51*4882a593Smuzhiyun u8 res3[0x44]; /* 0xac */ 52*4882a593Smuzhiyun u32 tcon1_io_polarity; /* 0xf0 */ 53*4882a593Smuzhiyun u32 tcon1_io_tristate; /* 0xf4 */ 54*4882a593Smuzhiyun u8 res4[0x108]; /* 0xf8 */ 55*4882a593Smuzhiyun u32 mux_ctrl; /* 0x200 */ 56*4882a593Smuzhiyun u8 res5[0x1c]; /* 0x204 */ 57*4882a593Smuzhiyun u32 lvds_ana0; /* 0x220 */ 58*4882a593Smuzhiyun u32 lvds_ana1; /* 0x224 */ 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * LCDC register constants. 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun #define SUNXI_LCDC_X(x) (((x) - 1) << 16) 65*4882a593Smuzhiyun #define SUNXI_LCDC_Y(y) (((y) - 1) << 0) 66*4882a593Smuzhiyun #define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24) 67*4882a593Smuzhiyun #define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25) 68*4882a593Smuzhiyun #define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0) 69*4882a593Smuzhiyun #define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0) 70*4882a593Smuzhiyun #define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0) 71*4882a593Smuzhiyun #define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31) 72*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4)) 73*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4)) 74*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111 75*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000 76*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111 77*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555 78*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777 79*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) 80*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31) 81*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) 82*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28) 83*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) 84*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) 85*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) 86*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) 87*4882a593Smuzhiyun #ifdef CONFIG_SUNXI_GEN_SUN6I 88*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20) 89*4882a593Smuzhiyun #else 90*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */ 91*4882a593Smuzhiyun #endif 92*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) 93*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) 94*4882a593Smuzhiyun #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) 95*4882a593Smuzhiyun #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) 96*4882a593Smuzhiyun #define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20) 97*4882a593Smuzhiyun #define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) 98*4882a593Smuzhiyun #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) 99*4882a593Smuzhiyun #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) 100*4882a593Smuzhiyun #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) 101*4882a593Smuzhiyun #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16) 102*4882a593Smuzhiyun #define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0) 103*4882a593Smuzhiyun #define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0) 104*4882a593Smuzhiyun #define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4) 105*4882a593Smuzhiyun #define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4) 106*4882a593Smuzhiyun #ifdef CONFIG_SUNXI_GEN_SUN6I 107*4882a593Smuzhiyun #define SUNXI_LCDC_LVDS_ANA0 0x40040320 108*4882a593Smuzhiyun #define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) 109*4882a593Smuzhiyun #define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24) 110*4882a593Smuzhiyun #define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20) 111*4882a593Smuzhiyun #else 112*4882a593Smuzhiyun #define SUNXI_LCDC_LVDS_ANA0 0x3f310000 113*4882a593Smuzhiyun #define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) 114*4882a593Smuzhiyun #endif 115*4882a593Smuzhiyun #define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) 116*4882a593Smuzhiyun #define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun void lcdc_init(struct sunxi_lcdc_reg * const lcdc); 119*4882a593Smuzhiyun void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth); 120*4882a593Smuzhiyun void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, 121*4882a593Smuzhiyun const struct display_timing *mode, 122*4882a593Smuzhiyun int clk_div, bool for_ext_vga_dac, 123*4882a593Smuzhiyun int depth, int dclk_phase); 124*4882a593Smuzhiyun void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, 125*4882a593Smuzhiyun const struct display_timing *mode, 126*4882a593Smuzhiyun bool ext_hvsync, bool is_composite); 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #endif /* _LCDC_H */ 129