1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * GTBUS initialisation for sun9i 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH 5*4882a593Smuzhiyun * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _SUNXI_GTBUS_SUN9I_H 11*4882a593Smuzhiyun #define _SUNXI_GTBUS_SUN9I_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/types.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct sunxi_gtbus_reg { 16*4882a593Smuzhiyun u32 mst_cfg[36]; /* 0x000 */ 17*4882a593Smuzhiyun u8 reserved1[0x70]; /* 0x090 */ 18*4882a593Smuzhiyun u32 bw_wdw_cfg; /* 0x100 */ 19*4882a593Smuzhiyun u32 mst_read_prio_cfg[2]; /* 0x104 */ 20*4882a593Smuzhiyun u32 lvl2_mst_cfg; /* 0x10c */ 21*4882a593Smuzhiyun u32 sw_clk_on; /* 0x110 */ 22*4882a593Smuzhiyun u32 sw_clk_off; /* 0x114 */ 23*4882a593Smuzhiyun u32 pmu_mst_en; /* 0x118 */ 24*4882a593Smuzhiyun u32 pmu_cfg; /* 0x11c */ 25*4882a593Smuzhiyun u32 pmu_cnt[19]; /* 0x120 */ 26*4882a593Smuzhiyun u32 reserved2[0x94]; /* 0x16c */ 27*4882a593Smuzhiyun u32 cci400_config[3]; /* 0x200 */ 28*4882a593Smuzhiyun u32 cci400_status[2]; /* 0x20c */ 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* for register GT_MST_CFG_REG(n) */ 32*4882a593Smuzhiyun #define GT_ENABLE_REQ (1<<31) /* clock on */ 33*4882a593Smuzhiyun #define GT_DISABLE_REQ (1<<30) /* clock off */ 34*4882a593Smuzhiyun #define GT_QOS_SHIFT 28 35*4882a593Smuzhiyun #define GT_THD1_SHIFT 16 36*4882a593Smuzhiyun #define GT_REQN_MAX 0xf /* max no master requests in one cycle */ 37*4882a593Smuzhiyun #define GT_REQN_SHIFT 12 38*4882a593Smuzhiyun #define GT_THD0_SHIFT 0 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define GT_QOS_MAX 0x3 41*4882a593Smuzhiyun #define GT_THD_MAX 0xfff 42*4882a593Smuzhiyun #define GT_BW_WDW_MAX 0xffff 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* mst_read_prio_cfg */ 45*4882a593Smuzhiyun #define GT_PRIO_LOW 0 46*4882a593Smuzhiyun #define GT_PRIO_HIGH 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* GTBUS port ids */ 49*4882a593Smuzhiyun #define GT_PORT_CPUM1 0 50*4882a593Smuzhiyun #define GT_PORT_CPUM2 1 51*4882a593Smuzhiyun #define GT_PORT_SATA 2 52*4882a593Smuzhiyun #define GT_PORT_USB3 3 53*4882a593Smuzhiyun #define GT_PORT_FE0 4 54*4882a593Smuzhiyun #define GT_PORT_BE1 5 55*4882a593Smuzhiyun #define GT_PORT_BE2 6 56*4882a593Smuzhiyun #define GT_PORT_IEP0 7 57*4882a593Smuzhiyun #define GT_PORT_FE1 8 58*4882a593Smuzhiyun #define GT_PORT_BE0 9 59*4882a593Smuzhiyun #define GT_PORT_FE2 10 60*4882a593Smuzhiyun #define GT_PORT_IEP1 11 61*4882a593Smuzhiyun #define GT_PORT_VED 12 62*4882a593Smuzhiyun #define GT_PORT_VEE 13 63*4882a593Smuzhiyun #define GT_PORT_FD 14 64*4882a593Smuzhiyun #define GT_PORT_CSI 15 65*4882a593Smuzhiyun #define GT_PORT_MP 16 66*4882a593Smuzhiyun #define GT_PORT_HSI 17 67*4882a593Smuzhiyun #define GT_PORT_SS 18 68*4882a593Smuzhiyun #define GT_PORT_TS 19 69*4882a593Smuzhiyun #define GT_PORT_DMA 20 70*4882a593Smuzhiyun #define GT_PORT_NDFC0 21 71*4882a593Smuzhiyun #define GT_PORT_NDFC1 22 72*4882a593Smuzhiyun #define GT_PORT_CPUS 23 73*4882a593Smuzhiyun #define GT_PORT_TH 24 74*4882a593Smuzhiyun #define GT_PORT_GMAC 25 75*4882a593Smuzhiyun #define GT_PORT_USB0 26 76*4882a593Smuzhiyun #define GT_PORT_MSTG0 27 77*4882a593Smuzhiyun #define GT_PORT_MSTG1 28 78*4882a593Smuzhiyun #define GT_PORT_MSTG2 29 79*4882a593Smuzhiyun #define GT_PORT_MSTG3 30 80*4882a593Smuzhiyun #define GT_PORT_USB1 31 81*4882a593Smuzhiyun #define GT_PORT_GPU0 32 82*4882a593Smuzhiyun #define GT_PORT_GPU1 33 83*4882a593Smuzhiyun #define GT_PORT_USB2 34 84*4882a593Smuzhiyun #define GT_PORT_CPUM0 35 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define GP_MST_CFG_DEFAULT \ 87*4882a593Smuzhiyun ((GT_QOS_MAX << GT_QOS_SHIFT) | \ 88*4882a593Smuzhiyun (GT_THD_MAX << GT_THD1_SHIFT) | \ 89*4882a593Smuzhiyun (GT_REQN_MAX << GT_REQN_SHIFT) | \ 90*4882a593Smuzhiyun (GT_THD_MAX << GT_THD0_SHIFT)) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif 93