1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _SUNXI_DMA_SUN4I_H 8*4882a593Smuzhiyun #define _SUNXI_DMA_SUN4I_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct sunxi_dma_cfg 11*4882a593Smuzhiyun { 12*4882a593Smuzhiyun u32 ctl; /* 0x00 Control */ 13*4882a593Smuzhiyun u32 src_addr; /* 0x04 Source address */ 14*4882a593Smuzhiyun u32 dst_addr; /* 0x08 Destination address */ 15*4882a593Smuzhiyun u32 bc; /* 0x0C Byte counter */ 16*4882a593Smuzhiyun u32 res0[2]; 17*4882a593Smuzhiyun u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */ 18*4882a593Smuzhiyun u32 res1; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct sunxi_dma 22*4882a593Smuzhiyun { 23*4882a593Smuzhiyun u32 irq_en; /* 0x000 IRQ enable */ 24*4882a593Smuzhiyun u32 irq_pend; /* 0x004 IRQ pending */ 25*4882a593Smuzhiyun u32 auto_gate; /* 0x008 auto gating */ 26*4882a593Smuzhiyun u32 res0[61]; 27*4882a593Smuzhiyun struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */ 28*4882a593Smuzhiyun u32 res1[64]; 29*4882a593Smuzhiyun struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */ 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun enum ddma_drq_type { 33*4882a593Smuzhiyun DDMA_DST_DRQ_SRAM = 0, 34*4882a593Smuzhiyun DDMA_SRC_DRQ_SRAM = 0, 35*4882a593Smuzhiyun DDMA_DST_DRQ_SDRAM = 1, 36*4882a593Smuzhiyun DDMA_SRC_DRQ_SDRAM = 1, 37*4882a593Smuzhiyun DDMA_DST_DRQ_PATA = 2, 38*4882a593Smuzhiyun DDMA_SRC_DRQ_PATA = 2, 39*4882a593Smuzhiyun DDMA_DST_DRQ_NAND = 3, 40*4882a593Smuzhiyun DDMA_SRC_DRQ_NAND = 3, 41*4882a593Smuzhiyun DDMA_DST_DRQ_USB0 = 4, 42*4882a593Smuzhiyun DDMA_SRC_DRQ_USB0 = 4, 43*4882a593Smuzhiyun DDMA_DST_DRQ_ETHERNET_MAC_TX = 6, 44*4882a593Smuzhiyun DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7, 45*4882a593Smuzhiyun DDMA_DST_DRQ_SPI1_TX = 8, 46*4882a593Smuzhiyun DDMA_SRC_DRQ_SPI1_RX = 9, 47*4882a593Smuzhiyun DDMA_DST_DRQ_SECURITY_SYS_TX = 10, 48*4882a593Smuzhiyun DDMA_SRC_DRQ_SECURITY_SYS_RX = 11, 49*4882a593Smuzhiyun DDMA_DST_DRQ_TCON0 = 14, 50*4882a593Smuzhiyun DDMA_DST_DRQ_TCON1 = 15, 51*4882a593Smuzhiyun DDMA_DST_DRQ_MSC = 23, 52*4882a593Smuzhiyun DDMA_SRC_DRQ_MSC = 23, 53*4882a593Smuzhiyun DDMA_DST_DRQ_SPI0_TX = 26, 54*4882a593Smuzhiyun DDMA_SRC_DRQ_SPI0_RX = 27, 55*4882a593Smuzhiyun DDMA_DST_DRQ_SPI2_TX = 28, 56*4882a593Smuzhiyun DDMA_SRC_DRQ_SPI2_RX = 29, 57*4882a593Smuzhiyun DDMA_DST_DRQ_SPI3_TX = 30, 58*4882a593Smuzhiyun DDMA_SRC_DRQ_SPI3_RX = 31, 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) & 0x1f) 62*4882a593Smuzhiyun #define SUNXI_DMA_CTL_MODE_IO (1 << 5) 63*4882a593Smuzhiyun #define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 (2 << 9) 64*4882a593Smuzhiyun #define SUNXI_DMA_CTL_DST_DRQ(a) (((a) & 0x1f) << 16) 65*4882a593Smuzhiyun #define SUNXI_DMA_CTL_DST_DATA_WIDTH_32 (2 << 25) 66*4882a593Smuzhiyun #define SUNXI_DMA_CTL_TRIGGER (1 << 31) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* _SUNXI_DMA_SUN4I_H */ 69