1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Sunxi platform display controller register and constant defines 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Based on out of tree Linux DRM driver defines: 7*4882a593Smuzhiyun * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr> 8*4882a593Smuzhiyun * Copyright (c) 2016 Allwinnertech Co., Ltd. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef _SUNXI_DISPLAY2_H 14*4882a593Smuzhiyun #define _SUNXI_DISPLAY2_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* internal clock settings */ 17*4882a593Smuzhiyun struct de_clk { 18*4882a593Smuzhiyun u32 gate_cfg; 19*4882a593Smuzhiyun u32 bus_cfg; 20*4882a593Smuzhiyun u32 rst_cfg; 21*4882a593Smuzhiyun u32 div_cfg; 22*4882a593Smuzhiyun u32 sel_cfg; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* global control */ 26*4882a593Smuzhiyun struct de_glb { 27*4882a593Smuzhiyun u32 ctl; 28*4882a593Smuzhiyun u32 status; 29*4882a593Smuzhiyun u32 dbuff; 30*4882a593Smuzhiyun u32 size; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* alpha blending */ 34*4882a593Smuzhiyun struct de_bld { 35*4882a593Smuzhiyun u32 fcolor_ctl; 36*4882a593Smuzhiyun struct { 37*4882a593Smuzhiyun u32 fcolor; 38*4882a593Smuzhiyun u32 insize; 39*4882a593Smuzhiyun u32 offset; 40*4882a593Smuzhiyun u32 dum; 41*4882a593Smuzhiyun } attr[4]; 42*4882a593Smuzhiyun u32 dum0[15]; 43*4882a593Smuzhiyun u32 route; 44*4882a593Smuzhiyun u32 premultiply; 45*4882a593Smuzhiyun u32 bkcolor; 46*4882a593Smuzhiyun u32 output_size; 47*4882a593Smuzhiyun u32 bld_mode[4]; 48*4882a593Smuzhiyun u32 dum1[4]; 49*4882a593Smuzhiyun u32 ck_ctl; 50*4882a593Smuzhiyun u32 ck_cfg; 51*4882a593Smuzhiyun u32 dum2[2]; 52*4882a593Smuzhiyun u32 ck_max[4]; 53*4882a593Smuzhiyun u32 dum3[4]; 54*4882a593Smuzhiyun u32 ck_min[4]; 55*4882a593Smuzhiyun u32 dum4[3]; 56*4882a593Smuzhiyun u32 out_ctl; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* VI channel */ 60*4882a593Smuzhiyun struct de_vi { 61*4882a593Smuzhiyun struct { 62*4882a593Smuzhiyun u32 attr; 63*4882a593Smuzhiyun u32 size; 64*4882a593Smuzhiyun u32 coord; 65*4882a593Smuzhiyun u32 pitch[3]; 66*4882a593Smuzhiyun u32 top_laddr[3]; 67*4882a593Smuzhiyun u32 bot_laddr[3]; 68*4882a593Smuzhiyun } cfg[4]; 69*4882a593Smuzhiyun u32 fcolor[4]; 70*4882a593Smuzhiyun u32 top_haddr[3]; 71*4882a593Smuzhiyun u32 bot_haddr[3]; 72*4882a593Smuzhiyun u32 ovl_size[2]; 73*4882a593Smuzhiyun u32 hori[2]; 74*4882a593Smuzhiyun u32 vert[2]; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun struct de_ui { 78*4882a593Smuzhiyun struct { 79*4882a593Smuzhiyun u32 attr; 80*4882a593Smuzhiyun u32 size; 81*4882a593Smuzhiyun u32 coord; 82*4882a593Smuzhiyun u32 pitch; 83*4882a593Smuzhiyun u32 top_laddr; 84*4882a593Smuzhiyun u32 bot_laddr; 85*4882a593Smuzhiyun u32 fcolor; 86*4882a593Smuzhiyun u32 dum; 87*4882a593Smuzhiyun } cfg[4]; 88*4882a593Smuzhiyun u32 top_haddr; 89*4882a593Smuzhiyun u32 bot_haddr; 90*4882a593Smuzhiyun u32 ovl_size; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct de_csc { 94*4882a593Smuzhiyun u32 csc_ctl; 95*4882a593Smuzhiyun u8 res[0xc]; 96*4882a593Smuzhiyun u32 coef11; 97*4882a593Smuzhiyun u32 coef12; 98*4882a593Smuzhiyun u32 coef13; 99*4882a593Smuzhiyun u32 coef14; 100*4882a593Smuzhiyun u32 coef21; 101*4882a593Smuzhiyun u32 coef22; 102*4882a593Smuzhiyun u32 coef23; 103*4882a593Smuzhiyun u32 coef24; 104*4882a593Smuzhiyun u32 coef31; 105*4882a593Smuzhiyun u32 coef32; 106*4882a593Smuzhiyun u32 coef33; 107*4882a593Smuzhiyun u32 coef34; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 111*4882a593Smuzhiyun * DE register constants. 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun #define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000) 114*4882a593Smuzhiyun #define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define SUNXI_DE2_MUX_GLB_REGS 0x00000 117*4882a593Smuzhiyun #define SUNXI_DE2_MUX_BLD_REGS 0x01000 118*4882a593Smuzhiyun #define SUNXI_DE2_MUX_CHAN_REGS 0x02000 119*4882a593Smuzhiyun #define SUNXI_DE2_MUX_CHAN_SZ 0x1000 120*4882a593Smuzhiyun #define SUNXI_DE2_MUX_VSU_REGS 0x20000 121*4882a593Smuzhiyun #define SUNXI_DE2_MUX_GSU1_REGS 0x30000 122*4882a593Smuzhiyun #define SUNXI_DE2_MUX_GSU2_REGS 0x40000 123*4882a593Smuzhiyun #define SUNXI_DE2_MUX_GSU3_REGS 0x50000 124*4882a593Smuzhiyun #define SUNXI_DE2_MUX_FCE_REGS 0xa0000 125*4882a593Smuzhiyun #define SUNXI_DE2_MUX_BWS_REGS 0xa2000 126*4882a593Smuzhiyun #define SUNXI_DE2_MUX_LTI_REGS 0xa4000 127*4882a593Smuzhiyun #define SUNXI_DE2_MUX_PEAK_REGS 0xa6000 128*4882a593Smuzhiyun #define SUNXI_DE2_MUX_ASE_REGS 0xa8000 129*4882a593Smuzhiyun #define SUNXI_DE2_MUX_FCC_REGS 0xaa000 130*4882a593Smuzhiyun #define SUNXI_DE2_MUX_DCSC_REGS 0xb0000 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define SUNXI_DE2_FORMAT_XRGB_8888 4 133*4882a593Smuzhiyun #define SUNXI_DE2_FORMAT_RGB_565 10 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0) 136*4882a593Smuzhiyun #define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0) 137*4882a593Smuzhiyun #define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1)) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif /* _SUNXI_DISPLAY2_H */ 142