1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuration settings for the Allwinner A64 (sun50i) CPU 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD) 8*4882a593Smuzhiyun /* reserve space for BOOT0 header information */ 9*4882a593Smuzhiyun b reset 10*4882a593Smuzhiyun .space 1532 11*4882a593Smuzhiyun #elif defined(CONFIG_ARM_BOOT_HOOK_RMR) 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Switch into AArch64 if needed. 14*4882a593Smuzhiyun * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun tst x0, x0 // this is "b #0x84" in ARM 17*4882a593Smuzhiyun b reset 18*4882a593Smuzhiyun .space 0x7c 19*4882a593Smuzhiyun .word 0xe59f1024 // ldr r1, [pc, #36] ; 0x170000a0 20*4882a593Smuzhiyun .word 0xe59f0024 // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE 21*4882a593Smuzhiyun .word 0xe5810000 // str r0, [r1] 22*4882a593Smuzhiyun .word 0xf57ff04f // dsb sy 23*4882a593Smuzhiyun .word 0xf57ff06f // isb sy 24*4882a593Smuzhiyun .word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR 25*4882a593Smuzhiyun .word 0xe3800003 // orr r0, r0, #3 26*4882a593Smuzhiyun .word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR 27*4882a593Smuzhiyun .word 0xf57ff06f // isb sy 28*4882a593Smuzhiyun .word 0xe320f003 // wfi 29*4882a593Smuzhiyun .word 0xeafffffd // b @wfi 30*4882a593Smuzhiyun .word 0x017000a0 // writeable RVBAR mapping address 31*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 32*4882a593Smuzhiyun .word CONFIG_SPL_TEXT_BASE 33*4882a593Smuzhiyun #else 34*4882a593Smuzhiyun .word CONFIG_SYS_TEXT_BASE 35*4882a593Smuzhiyun #endif 36*4882a593Smuzhiyun #else 37*4882a593Smuzhiyun /* normal execution */ 38*4882a593Smuzhiyun b reset 39*4882a593Smuzhiyun #endif 40